Frame buffer addressing scheme

• US 6,836,272 B2
• Filed: 03/12/2002
• Issued: 12/28/2004
• Est. Priority Date: 03/12/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lavelle, Michael G., Ing, Elena M., Leung, Philip C.
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US10/096,066
• Publication Number:
  US 20030174137A1
• Time in Patent Office: 1,022 Days
• Field of Search: 345/503, 345/520, 345/531, 345/540, 345/545, 345/564, 345/571, 345/572
• US Class Current: 345/540
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A graphics system includes a frame buffer that includes one or more memory devices and a frame buffer interface coupled to the frame buffer. Each memory device in the frame buffer includes N banks. Each of the N banks includes multiple pages, and each page is configured to store data corresponding to a portion of a screen region. The frame buffer interface is configured to generate address used to store data corresponding to a frame of data in the frame buffer. The frame includes multiple screen regions. The frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer. The addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions.

Claims

1. A graphics system comprising:

a frame buffer comprising one or more memory devices, wherein each memory device comprises N banks, wherein each of the N banks includes a plurality of pages, wherein each page is configured to store data corresponding to a portion of a screen region; and

a frame buffer interface coupled to the frame buffer and configured to generate address used to store data corresponding to a frame in the frame buffer, wherein the frame includes a plurality of screen regions, wherein the frame buffer interface is configured to generate addresses corresponding to the data and to provide the addresses to the frame buffer;

wherein the addresses are generated such that each of the N banks stores data corresponding to a portion of one out of every N screen regions within a horizontal group of screen regions, wherein a first screen region and a second screen region of the plurality of screen regions are horizontally neighboring screen regions, wherein the addresses are generated such that data corresponding to a portion of the first screen region is stored in a first one of the N banks and data corresponding to a portion of the second screen region is stored in a second one of the N banks.

2. The graphics system of claim 1, wherein each screen region included in the frame includes more pixels in a horizontal direction than in a vertical direction.

3. The graphics system of claim 1, wherein each screen region included in the frame is stored in a frame buffer page, wherein the frame buffer includes a plurality of memory devices, and wherein each frame buffer page includes a page from each memory device in the plurality of memory devices.

4. The graphics system of claim 1, wherein the frame buffer interface is configured to generate addresses so that each of the N banks stores data corresponding to a portion of one out of every two screen regions in a vertical group of screen regions, wherein a third screen region and a fourth screen region of the plurality of screen regions are vertically neighboring screen regions, and wherein the addresses are generated such that data corresponding to a portion of the third screen region is stored in a third one of the N banks and data corresponding to a portion of the fourth screen region is stored in a fourth one of the N banks.

5. The graphics system of claim 1, wherein the frame buffer interface is configured to generate address so that each of the N banks stores data corresponding to a portion of one out of every N screen regions in a vertical group of screen regions, wherein a third screen region and a fourth screen region of the plurality of screen regions are vertically neighboring screen regions, and wherein the addresses are generated such that data corresponding to a portion of the third screen region is stored in a third one of the N banks and data corresponding to a portion of the fourth screen region is stored in a fourth one of the N banks.

6. The graphics system of claim 1, wherein the frame buffer includes a plurality of serial access memories, wherein each of the serial access memories is coupled to receive data from a corresponding group of the N banks, wherein the frame buffer interface is configured to generate addresses so that data corresponding to different portions of horizontally neighboring screen regions is stored in different groups of the N banks.

7. The graphics system of claim 1, wherein the frame buffer interface is configured to prefetch the requested data from the frame buffer.

8. A method of operating a graphics system, the method comprising:

receiving a request for requested data stored in a frame buffer configured to store a frame of image data, wherein the frame comprises a plurality of screen regions, wherein the frame buffer includes one or more memory devices, wherein each memory device includes N banks, wherein each bank includes a plurality of pages each configured to store at least a portion of a screen region of the plurality of screen regions;

in response to said receiving, generating one or more addresses for the requested data; and

providing the one or more addresses generated by said generating to the frame buffer;

wherein said generating comprises generating addresses so that each of the N banks stores a portion of one out of every N screen regions, wherein portions of horizontally neighboring screen regions are stored in different ones of the N banks.

9. The method of claim 8, wherein each screen region includes more pixels in a horizontal direction than in a vertical direction.

10. The method of claim 8, wherein each screen region is stored in a frame buffer page, wherein the frame buffer includes a plurality of memory devices, and wherein each frame buffer page includes a page from each memory device in the plurality of memory devices.

11. The method of claim 8, wherein said generating comprises generating address so that each of the N banks stores a portion of one out of every two screen regions in a vertical group of screen regions and so that portions of vertically neighboring screen regions are stored in different ones of the N banks.

12. The method of claim 8, wherein said generating comprises generating addresses so that each of the N banks stores at least a portion of one out of every N screen regions in a vertical group of screen regions and so that portions of vertically neighboring screen regions are stored in different ones of the N banks.

13. The method of claim 8, wherein the frame buffer includes a plurality of serial access memories, wherein each of the serial access memories is coupled to receive data from a corresponding group of the N banks, wherein said generating comprises generating addresses so that portions of horizontally neighboring screen regions are stored in different groups of the N banks.

14. The method of claim 8, further comprising prefetching the requested data from the frame buffer.

15. The method of claim 8, wherein said generating comprises generating addresses dependent on a current sampling mode, wherein a footprint of each frame buffer block in the current sampling mode fits within a maximum frame buffer block footprint.