Combined single-ended and differential signaling interface
DC CAFCFirst Claim
1. A data interface circuit comprising:
- a first single-ended interface connected to a first signal output line;
a second single-ended interface connected to a second signal output line; and
a differential interface having a normal signal output connected to the first output line and a complementary signal output connected to the second signal output line;
wherein an output of the data interface circuit is selectable between a single-ended interface output and a differential interface output.
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Accused Products
Abstract
A data interface for CMOS imagers is disclosed that can be either a single-ended interface or a differential interface. The single-ended interface provides compatibility with many existing external devices. Further providing a differential interface allows a lower noise and a lower power interface for external devices that can support a differential signal. The combined single-ended and differential signal interface does not increase the number of pins required for a single-ended only interface. The data transfer width is set to the word width, which allows a fixed timing relationship between the clock edge and data transfer in both single-ended and differential modes. In single-ended mode, the data is transferred once per clock, but in the differential mode, the data is transferred twice per clock, once on each clock edge. This fixed timing relationship eliminates the need for and cost of explicit bit synchronization.
56 Citations
19 Claims
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1. A data interface circuit comprising:
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a first single-ended interface connected to a first signal output line;
a second single-ended interface connected to a second signal output line; and
a differential interface having a normal signal output connected to the first output line and a complementary signal output connected to the second signal output line;
wherein an output of the data interface circuit is selectable between a single-ended interface output and a differential interface output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A CMOS imaging apparatus comprising:
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a CMOS image sensor, the sensor having a data interface circuit comprising;
a first single-ended interface connected to a first signal output line;
a second single-ended interface connected to a second signal output line; and
a differential interface having a normal signal output connected to the first output line and a complementary signal output connected to the second signal output line;
wherein an output of the data interface circuit is selectable between a single-ended interface output and a differential interface output; and
an image processor connected to the CMOS image sensor to receive the signals output by the data interface circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An image processing method comprising the steps of:
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forming an analog image signal using a plurality of CMOS image sensing pixels;
converting the analog image signal to form a plurality of digital output signals;
transferring the digital output signals through either a single-ended or a differential interface circuit, as selected, to a digital image processor;
wherein when the single-ended output is selected, one bit is transferred per clock cycle on each signal output line, and when the differential output is selected, one half of the total output bits are transferred on a first edge of a clock, and a second halt of the output bits are transferred on a second edge of the clock, using the same total number of pins as used in by the single-ended interface. - View Dependent Claims (18, 19)
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Specification