Emulation system employing serial test port and alternative data transfer protocol

• US 6,836,757 B1
• Filed: 01/14/2000
• Issued: 12/28/2004
• Est. Priority Date: 02/19/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Swoboda, Gary L.
• Primary Examiner(s): Homere, Jean R.
• Assistant Examiner(s): DAY, HERNG DER
• Application Number:
  US09/483,321
• Time in Patent Office: 1,810 Days
• Field of Search: 703/25, 703/23, 703/24, 703/28, 714/724, 370/510
• US Class Current: 703/25
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

Emulation communications via a test access port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules. One of the modules is selected for communication. Nonselected modules are made nonresponsive to data on the serial connection. The external emulation hardware supplies a serial signal having a first logic state for a number of cycles greater in number than a number of bits of the serial connection of registers to the test access port. The emulation hardware supplies a start bit having an opposite logic state. The selected module detects the start bit and stores the next predetermined number of data bits. These bits could be data bits to be stored in a program visible data register or bits interpreted as an instruction for execution by the module. The selected module may transmit return communications via the serial scan path using the same format.

Claims

1. A method for emulation communications via a test data input port and boundary-scan architecture providing serial access to a serial connection of a plurality of registers disposed in a plurality of modules, each of the plurality of modules including at least one of the plurality of registers, comprising the steps of:

selecting for communication one of said plurality of modules, nonselected modules being nonresponsive to data on said serial connection;

supplying to the test data input port for communication to the boundary-scan architecture a serial signal having a number of bits greater in number than a number of bits of the serial connection of the plurality of registers, each bit of said serial signal having a first digital state;

following supply of said serial signal, supplying to the test data input port for communication to the boundary-scan architecture a single start bit having a second digital state opposite to said first digital state followed by a predetermined number of data bits;

at said selected module detecting said single start bit within the boundary-scan architecture and storing said predetermined number of data bits.

2. The method of claim 1, wherein:

said step of storing said predetermined number of data bits consists of storing said predetermined number of data bits in a program visible data register.

3. The method of claim 1, further comprising:

at said selected module, interpreting said predetermined number of data bits as an instruction and performing a function corresponding to said instruction.

4. The method of claim 1, wherein the boundary-scan architecture includes a test data output port following a last of the serial connection of registers, the method further comprising:

at said selected module, identifying a predetermined number of data bits to be transmitted, supplying to following registers in the serial connection of the plurality of registers a single start bit having a second digital state opposite to said first digital state followed by said identified predetermined number of data bits to be transmitted.

5. The method of claim 1, wherein:

said first digital state is 1; and

said second digital state is 0.

6. A digital electronic module comprising:

a serial scan path having a serial input and a serial output and connecting through a plurality of data registers within the digital electronic module;

a start bit detector having a start bit detector input, a start bit detector output and an alternative data output, said start bit detector monitoring serial data received at said start bit detector input and coupling serial data received at said start bit detector input to said start bit detector output except upon detection of a number of serial, bits having a first digital state followed by a single start bit having a second digital state opposite to said first digital state coupling a second predetermined number of bits of serial data received at said start bit detector input to said alternative data output;

an alternative data input register connected to said alternative data output of said start bit detector for receiving and storing data output by said start bit detector on said alternative data output;

an input switch having a serial test data input and a first mode input, said input switch connecting said serial test data input to said serial input of said serial scan path upon receiving a serial scan path mode signal at said first mode input and connecting said serial test data input to said start bit detector input of said start bit detector upon receiving an alternate data transfer protocol mode signal at said first mode input; and

an output switch having a test data output and a second mode input, said output switch connecting said serial output of said serial scan path to said test data output upon receiving said serial scan path mode signal on said second mode input and connecting said start bit detector output of said start bit detector to said test data output upon receiving said alternate data transfer protocol mode signal at said second mode input.

7. The digital electronic module of claim 6, wherein:

said first digital state is 1; and

said second digital state is 0.

8. The digital electronic module of claim 6, further comprising:

a bypass path connecting said input switch and said output switch;

said input switch further connecting said serial test data input to said bypass path upon receiving a bypass path mode signal at said first mode input; and

said output switch further connecting said bypass path to said test data output upon receiving said bypass path mode signal at said second mode input.

9. The digital electronic module of claim 6, further comprising:

a digital circuit connected to said alternative data input register operable to employ data stored in said alternative data input register.

10. The digital electronic module of claim 9, wherein:

said digital circuit includes a programmable digital processor core.

11. The digital electronic module of claim 10, wherein:

said programmable digital processor core employs data stored in said alternative data input register as an instruction controlling execution by said programmable digital processor core.

12. The digital electronic module of claim 9, further comprising:

an alternative data output register connected to said digital circuit storing data specified by said digital circuit;

a start bit generator connected to said alternative data output register and said output switch, said start bit generator generating a start bit having said second digital state followed by a a predetermined number of bits of output data stored in said alternative data output register; and

said output switch further connecting said start bit and said predetermined number of bits of output data stored in said alternative data output register to said test data output upon receiving a data transmission mode signal at said second mode input.