Layered crossbar for interconnection of multiple processors and shared memories

• US 6,836,815 B1
• Filed: 08/08/2001
• Issued: 12/28/2004
• Est. Priority Date: 07/11/2001
• Status: Expired due to Term

• Current Assignee: Mind Fusion, LLC (Ascend Innovation Management, LLC)
• Original Assignee: Pasternak Solutions LLC (Intellectual Ventures LLC)
• Inventors: Purcell, Stephen Clark, Cheng, Christopher Thomas
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US09/925,137
• Time in Patent Office: 1,238 Days
• Field of Search: 710/317, 710/100, 710/316, 703/1, 716/1, 370/381, 370/351, 370/362, 709/213, 709/249, 712/11, 712/20, 712/35, 340/2.28, 382/276, 358/444, 358/462, 711/148
• US Class Current: 710/317
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.

Claims

1. An apparatus comprising:

a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar;

a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar;

a plurality of memory groups each having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbars in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group; and

a plurality of memory chips each having a plurality of memory tracks each having a plurality of shared memory banks, each memory track connected to a different one of the memory controllers.

2. A method comprising:

implementing a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar;

implementing a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars;

connecting each switch crossbar to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar;

implementing a plurality of memory groups each having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar;

connecting each memory crossbar in each memory group to all of the switch crossbars in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group;

implementing a plurality of memory chips each having a plurality of memory tracks each having a plurality of shared memory banks; and

connecting each memory track to a different one of the memory controllers.

3. An apparatus for use in a scalable graphics system comprising:

a processor switch chip having a plurality of processors each connected to a processor crossbar; and

a memory switch chip having a plurality of memory controllers each connected to a memory crossbar and controlling a shared memory bank; and

wherein

the memory crossbar is connected to the processor crossbar.

4. The apparatus of claim 3, wherein each memory controller is connected to a memory chip having a shared memory bank.

5. The apparatus of claim 3, wherein the memory switch chip comprises a memory bank connected to the memory controller.

6. The apparatus of claim 3, wherein the apparatus is used for the purposes of ray-tracing.

7. A method comprising:

implementing a processor switch chip having a plurality of processors each connected to a processor crossbar;

implementing a memory switch chip having a plurality of memory controllers each connected to a memory crossbar and controlling a shared memory bank; and

connecting the memory crossbar to the processor crossbar.

8. The method of claim 7, further comprising:

implementing a memory chip having a shared memory bank; and

connecting each memory chip to one of the memory controllers.

9. The method of claim 7, wherein the memory switch chip comprises a memory bank connected to the memory controller.

10. An apparatus for use in a scalable graphics system comprising:

a processor switch chip having a plurality of processors each connected to a processor crossbar; and

a memory switch chip having a plurality of memory controllers each connected to a memory crossbar and controlling a shared memory bank, wherein

the memory crossbar is connected to the processor crossbar; and

an intermediate switch chip having a switch crossbar, the switch crossbar connected between the processor crossbar and the memory crossbar.

11. The apparatus of claim 10, wherein each memory controller is connected to a memory chip having a shared memory bank.

12. The apparatus of claim 10, wherein the memory switch chip comprises a memory bank connected to the memory controller.

13. The apparatus of claim 10, wherein the apparatus is used for the purposes of ray-tracing.

14. A method comprising:

implementing a processor switch chip having a plurality of processors each connected to a processor crossbar;

implementing a memory switch chip having a plurality of memory controllers each connected to a memory crossbar and controlling a shared memory bank;

connecting the memory crossbar to the processor crossbar;

implementing an intermediate switch chip having a switch crossbar; and

connecting the switch crossbar between the processor crossbar and the memory crossbar.

15. The method of claim 14, further comprising:

implementing a memory chip having a shared memory bank; and

connecting each memory chip to one of the memory controllers.

16. The method of claim 14, wherein the memory switch chip comprises a memory bank connected to the memory controller.