×

Layered crossbar for interconnection of multiple processors and shared memories

  • US 6,836,815 B1
  • Filed: 08/08/2001
  • Issued: 12/28/2004
  • Est. Priority Date: 07/11/2001
  • Status: Expired due to Term
First Claim
Patent Images

1. An apparatus comprising:

  • a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar;

    a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar;

    a plurality of memory groups each having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbars in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group; and

    a plurality of memory chips each having a plurality of memory tracks each having a plurality of shared memory banks, each memory track connected to a different one of the memory controllers.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×