Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

• US 6,836,839 B2
• Filed: 03/22/2001
• Issued: 12/28/2004
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QuickSilver Controls, Inc.
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): Pan, Daniel H.
• Application Number:
  US09/815,122
• Publication Number:
  US 20020138716A1
• Time in Patent Office: 1,377 Days
• Field of Search: 712/15, 712/17, 712/18, 712/29, 712/221, 712/225, 712/227, 712/41, 712/20, 712/10, 712/11, 712/13, 712/14, 712/16, 712/201, 710/312, 710/315, 326/41, 326/38, 326/39, 708/232, 379/185, 700/113
• US Class Current: 712/29
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An adaptive computing integrated circuit, comprising:

a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information;

a second plurality of heterogeneous computational elements, the second plurality of heterogeneous computational elements having a different set of computational elements than the first plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable, independently from the configuration and reconfiguration of the first plurality of heterogeneous computational elements by the first interconnection network, of configuring the second plurality of heterogeneous computational elements for a third functional mode of the plurality of functional modes in response to third configuration information, and of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes; and

a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements.

2. The adaptive computing integrated circuit of claim 1, wherein the first, second, third and fourth fixed architectures are selected from a plurality of specific architectures, the plurality of specific architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

3. The adaptive computing integrated circuit of claim 1, wherein the plurality of functional modes comprises at least two of the following functional modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

4. The adaptive computing integrated circuit of claim 1, wherein the first, second, third and fourth are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

5. The adaptive computing integrated circuit of claim 1, wherein the interconnection network reconfigurably routes a plurality of configuration information to or between the first and second pluralities of heterogeneous computational elements.

6. The adaptive computing integrated circuit of claim 1, wherein the first configuration information, the second configuration information, the third configuration information and the fourth configuration information are commingled with data to form a singular bit stream.

7. The adaptive computing integrated circuit of claim 1, further comprising:

a controller coupled to the first and second pluralities of heterogeneous computational elements and to the third interconnection network, the controller capable of directing and scheduling the configurations and reconfigurations of the first and second pluralities of heterogeneous computational elements for the plurality of functional modes.

8. The adaptive computing integrated circuit of claim 7, wherein the controller is further capable of timing and scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements with corresponding data.

9. The adaptive computing integrated circuit of claim 7, wherein the controller is further capable of selecting the first configuration information, the second configuration information, the third configuration information, and the fourth configuration information from a singular bit stream containing data commingled with a plurality of configuration information.

10. The adaptive computing integrated circuit of claim 1, further comprising:

a memory coupled to the first and second pluralities of heterogeneous computational elements and to the third interconnection network, the memory capable of storing the first configuration information, the second configuration information, the third configuration information and the fourth configuration information.

11. The adaptive computing integrated circuit of claim 1, wherein the first and second pluralities of heterogeneous computational elements are configured and reconfigured respectively through the first and second interconnection network, and in response to a plurality of configuration information, to implement a plurality of logic functions of a data flow graph.

12. The adaptive computing integrated circuit of claim 1, wherein the first and second interconnection networks are further configured to perform a plurality of logic decisions of a data flow graph.

13. The adaptive computing integrated circuit of claim 1, wherein the first and second pluralities of heterogeneous computational elements may be configured to form a plurality of adaptive and heterogeneous computational units.

14. The adaptive computing integrated circuit of claim 13, wherein each computation unit of the plurality of heterogeneous computation units further comprises:

a computational unit controller coupled to the first or second plurality of heterogeneous computational elements, the computational unit controller responsive to a plurality of configuration information to generate a plurality of control bits;

a plurality of input multiplexers, the plurality of input multiplexers responsive to the plurality of control bits to select an input line from the interconnection network for the reception of input information; and

a plurality of output demultiplexers, the plurality of output demultiplexers responsive to the plurality of control bits to select a plurality of output lines from the respective first or second interconnection network for the transfer of output information.

15. The adaptive computing integrated circuit of claim 13, wherein the plurality of computation units is configured to form a plurality of reconfigurable matrices.

16. The adaptive computing integrated circuit of claim 1 wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

17. The adaptive computing integrated circuit of claim 16, wherein the plurality of operating modes of the mobile terminal comprises at least two of the following modes:

a mobile telecommunication mode, a personal digital assistance mode, a multimedia reception mode, a mobile packet-based communication mode, and a paging mode.

18. A method for adaptive computing comprising:

in response to a first plurality of configuration information, configuring and reconfiguring through a first interconnection network a first plurality of heterogeneous computational elements for a first plurality of functional modes, the first plurality of heterogeneous computational elements forming a first reconfigurable architecture;

in response to a second plurality configuration information, independently configuring and reconfiguring through a second interconnection network a second plurality of heterogeneous computational elements for a second plurality of functional modes, the second plurality of heterogeneous computational elements forming a second reconfigurable architecture, wherein the second plurality of functional modes are different from the first plurality of functional modes and wherein the second reconfigurable architecture is different from the first reconfigurable architecture; and

reconfigurably routing, through a third interconnection network data and control information to and from the first and second pluralities of heterogeneous computational elements.

19. The adaptive computing method of claim 18, wherein the first and second pluralities of heterogeneous computational elements each comprise a plurality of fixed architectures, the plurality of fixed architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

20. The adaptive computing method of claim 18, wherein the first and second pluralities plurality of functional modes each comprise at least two of the following functional modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations and bit-level manipulations.

21. The adaptive computing method of claim 18, wherein the first and second pluralities of heterogeneous computational elements are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

22. The adaptive computing method of claim 18, further comprising:

reconfigurably routing, through the third interconnection network, data a plurality of configuration information to or between the first and second pluralities heterogeneous computational elements.

23. The adaptive computing method of claim 18, wherein the first and second pluralities of configuration information are commingled with data to form a singular bit stream.

24. The adaptive computing method of claim 18, further comprising:

directing and scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements for the first and second pluralities of functional modes.

25. The adaptive computing method of claim 18, further comprising:

timing and scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements with corresponding data.

26. The adaptive computing method of claim 18, further comprising:

selecting the first and second pluralities of configuration information from a singular bit stream comprising data commingled with configuration information.

27. The adaptive computing method of claim 18, further comprising:

storing in a memory the first and second pluralities of configuration information.

28. The adaptive computing method of claim 18, wherein the first and second pluralities plurality of heterogeneous computational elements are configured and reconfigured through the respective first and second interconnection network, and in response to the respective first and second pluralities of configuration information, to implement a plurality of logic functions of a data flow graph.

29. The adaptive computing method of claim 18, wherein the first and second interconnection networks are further configured to perform a plurality of logic decisions of a data flow graph.

30. The adaptive computing method of claim 18, further comprising:

generating a plurality of control bits;

in response to the plurality of control bits, selecting an input line from the first or second interconnection networks for the reception of input information; and

in response to the plurality of control bits, selecting an output line from the respective first or second interconnection network for the transfer of output information.

31. The adaptive computing method of claim 18, wherein the adaptive computing method is operable within a mobile terminal having a plurality of operating modes.

32. The adaptive computing method of claim 31, wherein the plurality of operating modes of the mobile terminal comprises at least two of the following modes:

a mobile telecommunication mode, a personal digital ass stance mode, a multimedia reception mode, a mobile packet-based communication mode, and a paging mode.

33. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous reconfigurable matrices comprising at least two distinct and different matrix architectures, each heterogeneous reconfigurable matrix of the plurality of heterogeneous reconfigurable matrices comprising a plurality of heterogeneous computation units, wherein each of the plurality of heterogeneous computation units are formed from a selected configuration, of a plurality of configurations, of a plurality of fixed computational elements, a first computational element of the plurality of fixed computational elements having a first fixed architecture and a second computational element of the plurality of fixed computational elements having a second fixed architecture, wherein the first fixed architecture is different from the second fixed architecture, and wherein each of the plurality of heterogeneous computation units is coupled to a corresponding first interconnect network and configurable and reconfigurable in response to a first plurality of configuration information for a corresponding plurality of functional modes and

a second interconnection network coupled to the plurality of heterogeneous reconfigurable matrices, the second matrix interconnection network capable of configuring and reconfiguring the plurality of heterogeneous reconfigurable matrices in response to a second plurality of configuration information for a corresponding plurality of operating modes.

34. The adaptive computing integrated circuit of claim 33, wherein each computation unit of the plurality of heterogeneous computation units is selectively reconfigurable and capable of executing a distinct algorithm of a plurality of algorithms.

35. The adaptive computing integrated circuit of claim 33, further comprising:

a controller coupled to the plurality of heterogeneous reconfigurable matrices, the controller capable of providing the first and second pluralities of configuration information to the heterogeneous reconfigurable matrices and to the second interconnection network.

36. The adaptive computing integrated circuit of claim 35, wherein the controller is further capable of detecting and selecting the first and second pluralities of configuration information from a singular input bit stream comprised of commingled data and the first and second pluralities of configuration information.

37. The adaptive computing integrated circuit of claim 35, wherein the controller is embodied as a predetermined configuration of a heterogeneous reconfigurable matrix of the plurality of heterogeneous reconfigurable matrices.

38. The adaptive computing integrated circuit of claim 35, wherein the controller is further capable of directing and scheduling the configuration and reconfiguration of the plurality of fixed computational elements for the plurality of functional modes.

39. The adaptive computing integrated circuit of claim 35, wherein the controller is further capable of timing and scheduling the configuration and reconfiguration of the plurality of fixed computational elements using corresponding data.

40. The adaptive computing integrated circuit of claim 35, further comprising:

a memory coupled to the controller and to the plurality of heterogeneous reconfigurable matrices, the memory capable of storing the first and second pluralities of configuration information.

41. The adaptive computing integrated circuit of claim 40, wherein the memory is embodied as a predetermined configuration of a heterogeneous reconfigurable matrix of the plurality of heterogeneous reconfigurable matrices.

42. The adaptive computing integrated circuit of claim 33, wherein the plurality of operating modes comprises a first operating mode and a second operating mode, the first operating mode being different than the second operating mode.

43. The adaptive computing integrated circuit of claim 33, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

44. The adaptive computing integrated circuit of claim 33, wherein the plurality of operating modes comprises at least two of the following operating modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

45. The adaptive computing integrated circuit of claim 33, wherein the first fixed architecture and the second fixed architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

46. The adaptive computing integrated circuit of claim 33, wherein the second interconnection network reconfigurably routes data and control information between and among the plurality of heterogeneous reconfigurable matrices.

47. The adaptive computing integrated circuit of claim 33, wherein the first and second pluralities of configuration information are commingled with data to form a singular bit stream.

48. An adaptive computing integrated circuit, comprising:

a first plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring and reconfiguring the first plurality of heterogeneous computational elements for a first plurality of functional modes in response to first plurality of configuration information;

a second plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring and reconfiguring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, wherein the first plurality of functional modes and the second plurality of functional modes are each different pluralities of functional modes;

a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements;

a third plurality of heterogeneous computational elements coupled to the third interconnection network, the third plurality of heterogeneous computational elements configured for a controller operating mode, the controller operating mode comprising functions for directing configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements, for selecting the first and second pluralities of configuration information from a singular bit stream comprising data commingled with the first and second pluralities of configuration information, and for scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements with corresponding data; and

a fourth plurality of heterogeneous computational elements coupled to the third interconnection network, the fourth plurality of heterogeneous computational elements configured for a memory operating mode for storing the first and second pluralities of configuration information.

49. The adaptive computing integrated circuit of claim 48, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of fixed architectures, the plurality of fixed architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

50. The adaptive computing integrated circuit of claim 48, wherein the first and second pluralities plurality of functional modes each comprise at least two of the following functional modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

51. The adaptive computing integrated circuit of claim 48, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

52. The adaptive computing integrated circuit of claim 51, wherein the plurality of operating modes of the mobile terminal comprises at least two of the following modes:

a mobile telecommunication mode, a personal digital assistance mode, a multimedia reception mode, a mobile packet-based communication mode, and a paging mode.

53. An adaptive computing integrated circuit, comprising:

a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture of a plurality of fixed architectures and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture of the plurality of fixed architectures, and the plurality of fixed architectures having functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information;

a second plurality of heterogeneous computational elements, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture of the plurality of fixed architectures and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture of the plurality of fixed architectures, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements for a third functional mode of a plurality of functional modes in response to third configuration information, and the second interconnection network further capable of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes of the plurality of functional modes;

a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements.

54. The adaptive computing integrated circuit of claim 53, wherein the plurality of functional modes comprises at least two of the following functional modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

55. The adaptive computing integrated circuit of claim 53, wherein the plurality of fixed architectures are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

56. The adaptive computing integrated circuit of claim 53, wherein the third interconnection network reconfigurably routes a plurality of configuration information to or between the first and second pluralities of heterogeneous computational elements.

57. The adaptive computing integrated circuit of claim 56, wherein the plurality of configuration information is commingled with data to form a singular bit stream.

58. The adaptive computing integrated circuit of claim 53, further comprising:

a controller coupled to the first and second pluralities of heterogeneous computational elements and to the third interconnection network, the controller capable of directing and scheduling the configuration of the first and second pluralities of heterogeneous computational elements for the plurality of functional modes.

59. The adaptive computing integrated circuit of claim 58, wherein the controller is further capable of timing and scheduling the configuration and reconfiguration of the first and second pluralities plurality of heterogeneous computational elements with corresponding data.

60. The adaptive computing integrated circuit of claim 59, wherein the controller is further capable of selecting the first, second, third and fourth configuration information from a singular bit stream comprising data commingled with a plurality of configuration information.

61. The adaptive computing integrated circuit of claim 53, further comprising:

a memory coupled to the first and second pluralities of heterogeneous computational elements and to the third interconnection network, the memory capable of storing the first, second, third and fourth configuration information.

62. The adaptive computing integrated circuit of claim 53, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

63. The adaptive computing integrated circuit of claim 62, wherein the plurality of operating modes of the mobile terminal comprises at least two of the following modes:

a mobile telecommunication mode, a personal digital assistance mode, a multimedia reception mode, a mobile packet-based communication mode, and a paging mode.

64. An adaptive computing integrated circuit, comprising:

a first plurality of heterogeneous computational elements, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for first functional mode of a plurality of functional modes in response to first configuration information, and the first interconnection network further capable of reconfiguring the first plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, and the plurality of functional modes comprising at least two of the following functional modes;

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations;

a second plurality of heterogeneous computational elements a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, wherein the first, second, third and fourth fixed architectures are each different fixed architectures;

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements or a third functional mode of a plurality of functional modes in response to third configuration information, and the second interconnection network further capable of reconfiguring the second plurality of heterogeneous computational elements for a fourth functional mode of the plurality of functional modes in response to fourth configuration information, wherein the first, second, third and fourth functional modes are each different functional modes of the plurality of functional modes; and

a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of selectively routing data and control information to and from the first and second pluralities of heterogeneous computational elements.

65. The adaptive computing integrated circuit of claim 64, wherein the first fixed architecture and the second fixed architecture are selected from a plurality of specific architectures, the plurality of specific architectures having functions for memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

66. The adaptive computing integrated circuit of claim 64, wherein the first fixed architecture and the second fixed architecture are selected to comparatively minimize power consumption of the adaptive computing integrated circuit.

67. The adaptive computing integrated circuit of claim 64, wherein the interconnection network reconfigurably routes a plurality of configuration information to or between the first and second pluralities of heterogeneous computational elements.

68. The adaptive computing integrated circuit of claim 67, wherein the plurality of configuration information is commingled with data to form a singular bit stream.

69. The adaptive computing integrated circuit of claim 64, further comprising:

a controller coupled to the first and second pluralities of heterogeneous computational elements and to the third interconnection network, the controller capable of directing and scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements for the plurality of functional modes.

70. The adaptive computing integrated circuit of claim 69, wherein the controller is further capable of timing and scheduling the configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements with corresponding data.

71. The adaptive computing integrated circuit of claim 69, wherein the controller is further capable of selecting a plurality of configuration information from a singular bit stream comprising data commingled with the plurality of configuration information.

72. The adaptive computing integrated circuit of claim 64, further comprising:

a memory coupled to the first and second pluralities of heterogeneous computational elements and to the interconnection network, the memory capable of storing a plurality of configuration information.

73. The adaptive computing integrated circuit of claim 64, wherein the adaptive computing integrated circuit is embodied within a mobile terminal having a plurality of operating modes.

74. The adaptive computing integrated circuit of claim 73, wherein the plurality of operating modes of the mobile terminal comprises at least two of the following modes:

a mobile telecommunication mode, a personal digital assistance mode, a multimedia reception mode, a mobile packet-based communication mode, and a paging mode.

75. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous computational elements, a first computational element of the plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;

an interconnection network coupled to the plurality of heterogeneous computational elements, the interconnection network capable of configuring the plurality of heterogeneous computational elements for a first functional mode of a plurality of functional modes in response to first configuration information, and the interconnection network further capable of reconfiguring the plurality of heterogeneous computational elements for a second functional mode of the plurality of functional modes in response to second configuration information, the first functional mode being different than the second functional mode;

a controller coupled to the plurality of heterogeneous computational elements, the controller responsive to a plurality of configuration information to generate a plurality of control bits;

a plurality of input multiplexers, the plurality of input multiplexers responsive to the plurality of control bits to select an input line from the interconnection network for the reception of input information; and

a plurality of output demultiplexers, the plurality of output demultiplexers responsive to the plurality of control bits to select a plurality of output lines from the interconnection network for the transfer of output information.

76. The adaptive computing integrated circuit of claim 75, wherein the first and second pluralities of heterogeneous computational elements are selected from a plurality of specific architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

77. An adaptive computing integrated circuit, comprising:

a first computational unit having a first plurality of heterogeneous computational elements forming a first reconfigurable architecture, a first computational element of the first plurality of heterogeneous computational elements having a first fixed architecture and a second computational element of the first plurality of heterogeneous computational elements having a second fixed architecture, the first fixed architecture being different than the second fixed architecture;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring the first plurality of heterogeneous computational elements for first plurality of functional modes in response to a first plurality of configuration information;

a second computational unit having a second plurality of heterogeneous computational elements forming a second reconfigurable architecture, the second reconfigurable architecture being different than the first reconfigurable architecture, a third computational element of the second plurality of heterogeneous computational elements having a third fixed architecture and a fourth computational element of the second plurality of heterogeneous computational elements having a fourth fixed architecture, the third fixed architecture being different than the fourth fixed architecture;

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, the second plurality of functional modes being different than the first plurality of functional modes;

a third interconnection network coupled to the first computational unit and to the second computational unit, the third interconnection network capable of selectively and reconfigurably routing data and control information to the first computational unit and to the second computational unit.

78. The adaptive computing integrated circuit of claim 77, wherein the data and control information are collectively embodied as a unitary data packet having a predetermined data structure.

79. The adaptive computing integrated circuit of claim 77, wherein the third interconnection network is further capable of configuring and reconfiguring the first computational unit and the second computational unit for a plurality of operational modes in response to a third plurality of configuration information.

80. The adaptive computing integrated circuit of claim 77, wherein the first and second pluralities of heterogeneous computational elements are selected from a plurality of fixed architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

81. The adaptive computing integrated circuit of claim 77, further comprising:

a controller coupled through the third interconnection network to the first computational unit and to the second computational unit, the controller capable of directing and scheduling the configuration and reconfiguration of the plurality of heterogeneous computational elements for the first and second pluralities of functional modes.

82. An adaptive computing integrated circuit, comprising:

a first plurality of heterogeneous computational elements forming a first reconfigurable architecture;

a first interconnection network coupled to the first plurality of heterogeneous computational elements, the first interconnection network capable of configuring and reconfiguring the first plurality of heterogeneous computational elements for a first plurality of functional modes in response to a first plurality of configuration information;

a second plurality of heterogeneous computational elements forming a second reconfigurable architecture, the second plurality of heterogeneous computational elements being different than the first plurality of heterogeneous computational elements, and the second reconfigurable architecture being different than the first reconfigurable architecture; and

a second interconnection network coupled to the second plurality of heterogeneous computational elements, the second interconnection network capable of configuring and reconfiguring the second plurality of heterogeneous computational elements for a second plurality of functional modes in response to a second plurality of configuration information, the second plurality of functional modes being different than the first plurality of functional modes.

83. The adaptive computing integrated circuit of claim 82, further comprising:

a third interconnection network coupled to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the third interconnection network capable of configuring and reconfiguring the first and second pluralities of heterogeneous computational elements for a plurality of operational modes in response to a third plurality of configuration information.

84. The adaptive computing integrated circuit of claim 83, wherein the third interconnection network is capable of selectively routing control information n to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements to direct and control the configuration and reconfiguration of the first plurality of heterogeneous computational elements and the second plurality of heterogeneous computational elements.

85. The adaptive computing integrated circuit of claim 83, wherein the third interconnection network is capable of selectively routing data to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements.

86. The adaptive computing integrated circuit of claim 83, further comprising;

a controller coupled through the third interconnection network to the first plurality of heterogeneous computational elements and to the second plurality of heterogeneous computational elements, the controller capable of directing and scheduling configuration and reconfiguration of the first and second pluralities of heterogeneous computational elements for the plurality of operational modes.

87. The adaptive computing integrated circuit of claim 83, wherein the first and second pluralities of heterogeneous computational elements are selected from a plurality of fixed architectures having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

88. The adaptive computing integrated circuit of claim 83, wherein the plurality of operational modes comprises at least two of the following operational modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

89. An adaptive computing integrated circuit, comprising:

a plurality of heterogeneous reconfigurable matrices, at least two heterogeneous reconfigurable matrices of the plurality of heterogeneous reconfigurable matrices comprised of distinct and different sets of a plurality of heterogeneous computational elements to form correspondingly distinct and different matrix architectures, each set of the plurality of heterogeneous computational elements coupled to a corresponding first interconnection network and configurable in response to first configuration information for a corresponding plurality of functional mode for performance of a corresponding and distinct algorithm by each of the at least two heterogeneous reconfigurable matrices; and

a matrix interconnection network coupled to the plurality of heterogeneous reconfigurable matrices, the matrix interconnection network capable of selectively and reconfigurably routing data and control to each heterogeneous reconfigurable matrix of the plurality of reconfigurable matrices, the matrix interconnection network further capable of configuring and reconfiguring the plurality of heterogeneous reconfigurable matrices, in response to second configuration information, for a plurality of operating modes.

90. The adaptive computing integrated circuit of claim 89, further comprising:

a controller coupled to the plurality of heterogeneous reconfigurable matrices, the controller capable of providing the first and second configuration information to the heterogeneous reconfigurable matrices and to the matrix interconnection network.

91. The adaptive computing integrated circuit of claim 90, wherein the controller is further capable of providing a unitary data and control packet to the matrix interconnection network for selective routing to the plurality of heterogeneous reconfigurable matrices, the unitary data and control packet having a predetermined data structure containing data and control information.

92. The adaptive computing integrated circuit of claim 89, wherein the plurality of heterogeneous computational elements are selected from a plurality of fixed architectures, the plurality of fixed architectures comprising fixed circuitry having at least two of the following corresponding functions:

memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability.

93. The adaptive computing integrated circuit of claim 89, wherein the plurality of operating modes comprises at least two of the following operating modes:

linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.