Circuit including a built-in self-test

• US 6,836,866 B2
• Filed: 10/22/2001
• Issued: 12/28/2004
• Est. Priority Date: 04/20/1999
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Dirscherl, Gerd, Gärtner, Wolfgang, Nolles, Jürgen
• Primary Examiner(s): Lamarre, Guy J.
• Assistant Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US10/007,391
• Publication Number:
  US 20020104052A1
• Time in Patent Office: 1,163 Days
• Field of Search: 714/733, 714/734, 714/728, 714/724, 714/726, 714/739, 714/742
• US Class Current: 714/733
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31719 Security aspects, e.g. preventing unauthorised access during test
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.

Claims

1. A built-in self-test circuit to be connected to an external device, the circuit comprising:

a logic circuit having a structure to be tested;

a structural testing device for testing said structure of said logic circuit;

a functional circuit connected to said structural testing device through an indirect interface, said functional circuit driving said logic circuit through a direct interface;

said functional circuit receiving test commands from the external device through a standard interface; and

said functional circuit at least partially forwarding the test commands to said indirect interface for indirectly driving said logic circuit.

2. The circuit according to claim 1, wherein said structural testing device includes one of the group consisting of a scan path and test points in said logic circuit tested.

3. The circuit according to claim 1, wherein:

said functional circuit stores test patterns in the form of vectors optimized to said logic circuit tested; and

said structural testing device utilizes said test patterns.

4. The circuit according to claim 3, wherein the external device loads said test patterns through the standard interface.

5. The circuit according to claim 1, wherein said structural testing device includes a test pattern generator for generating a test pattern in the form of pseudo-random vectors.

6. The circuit according to claim 5, wherein:

said functional circuit includes software; and

said structural testing device has a part realized as a portion of said software in said functional circuit.

7. The circuit according to claim 1, wherein said functional circuit includes a functional testing device for functionally testing said logic circuit through said direct interface.

8. The circuit according to claim 7, wherein said functional testing device performs a functional test based upon a simulation result for said structural test device and said logic circuit.

said structural testing device has a part realized as a portion of said software in said functional circuit.

9. The circuit according to claim 1, wherein said logic circuit tested includes logic modules.

10. The circuit according to claim 9, wherein said functional circuit selects at least one of said logic modules for testing.

11. The circuit according to claim 9, wherein said functional circuit tests at least one of said logic modules.

12. The circuit according to claim 1, wherein the standard interface is a contactless interface.

13. In a chip card, an integrated circuit comprising:

a built-in self-test circuit to be connected to an external device, said built-in self-test circuit having;

a logic circuit having a structure to be tested;

a structural testing device for testing said structure of said logic circuit;

a functional circuit connected to said structural testing device through an indirect interface, said functional circuit driving said logic circuit through a direct interface;

said functional circuit receiving test commands from the external device through a standard interface; and

said functional circuit at least partially forwarding the test commands to said indirect interface for indirectly driving said logic circuit.

14. A built-in self-test circuit to be connected to an external device, the circuit comprising:

a logic circuit having a structure to be tested;

a structural testing device for testing said structure of said logic circuit;

a functional circuit having a standard interface connecting said functional circuit to the external device transmitting test commands, said functional circuit receiving the test commands through said standard interface;

an indirect interface for indirectly driving said logic circuit, said indirect interface connecting said functional circuit to said structural testing device;

a direct interface connecting said functional circuit to said logic circuit, said functional circuit driving said logic circuit through said direct interface; and

said functional circuit at least partially forwarding the test commands to said indirect interface.