Automatic synthesis script generation for synopsys design compiler

• US 6,836,877 B1
• Filed: 02/20/1998
• Issued: 12/28/2004
• Est. Priority Date: 02/20/1998
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dupenloup, Guy
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/026,790
• Time in Patent Office: 2,503 Days
• Field of Search: 716/18, 716/3, 716/4, 716/8, 716/11, 716/5, 716/2, 395/500.19, 703/16
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A method of generating synthesis scripts to synthesize integrated circuit (IC) designs described in a generic netlist into a gate-level description includes the steps of identifying hardware elements in a generic netlist, determining key pins for each of the identified hardware elements, extracting design structure and hierarchy from the generic netlist, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design, and generating script to cause a logic synthesis tool to repeat these bottom-up and top-down applications until constraints are satisfied.

Claims

1. A method of generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, said method comprising the steps of:

causing a logic synthesis tool to generate a generic netlist from the RTL code description;

identifying hardware elements in the generic netlist;

determining key pins for each of said identified hardware elements;

extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements; and

generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said script includes instructions to cause the logic synthesis tool to;

apply bottom-up synthesis to modules and sub-modules of the IC design,

apply top-down characterization to modules and sub-modules of the IC design, and

repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

2. The method according to claim 1 wherein said step of extracting design structure allows for a multilevel structuring of modules of the IC design.

3. The method according to claim 1 wherein the script also causes the logic synthesis tool to apply an initial mapping to the IC design.

4. The method according to claim 1 wherein the logic synthesis tool is Synopsys Design Compiler.

5. The method according to claim 1 further comprising the step of rearranging the design hierarchy of the IC design.

6. The method according to claim 1 wherein the script also causes the logic synthesis tool to ungroup modules of the IC design.

7. The method according to claim 1, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.

8. An apparatus for generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, comprising:

a processor;

memory connected to said processor;

said memory having instructions for said processor to;

cause a logic synthesis tool to generate a generic netlist from the RTL code description;

identify hardware elements in the generic netlist;

determine key pins for each of said identified hardware elements;

extract design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements; and

generate script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said script includes instructions to cause the logic synthesis tool to;

apply bottom-up synthesis to modules and sub-modules of the design,

apply top-down characterization to modules and sub-modules of the IC design,

repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

9. The apparatus according to claim 8, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.

10. An apparatus for generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, comprising:

means for causing a logic synthesis tool to generate a generic netlist from the RTL code description;

means for identifying hardware elements in the generic netlist;

means for

determining key pins for each of said identified hardware elements;

means for extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements; and

means for generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said script includes instructions to cause the logic synthesis tool to;

apply bottom-up synthesis to modules and sub-modules of the IC design,

apply top-down characterization to modules and sub-modules of the IC design, and

repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

11. The apparatus according to claim 10, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.

12. A computer storage medium containing instructions for generating synthesis script to synthesize an integrated circuit (IC) design from a generic netlist into a gate-level description, said instructions comprising the steps of:

causing a logic synthesis tool to generate a generic netlist from the RTL code description;

identifying hardware elements in the generic netlist;

determining key pins for each of said identified hardware elements;

extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements; and

generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said script includes instructions to cause the logic synthesis tool to;

apply bottom-up synthesis to modules and sub-modules of the IC design,

apply top-down characterization to modules and sub-modules of the IC design, and

repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

13. The computer storage medium of claim 12 wherein said computer storage medium is selected from a group consisting of magnetic device, optical device, magneto-optical device, floppy diskette, CD-ROM, magnetic tape, computer hard drive, and memory card.

14. The computer storage medium according to claim 12, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.

15. A process for synthesizing an integrated circuit (IC) design from a RTL code description into a gate-level description, said process comprising the steps of:

generating a generic netlist from the RTL code description;

identifying hardware elements in the generic netlist;

determining key pins for the identified hardware elements in the generic netlist;

extracting design structure and design hierarchy from the generic netlist based on the identified hardware elements and the key pins;

synthesizing the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said synthesis of the IC design includes;

applying bottom-up synthesis to modules and sub-modules of the IC design,

applying top-down characterization to modules and sub-modules of the IC design, and

repeating said bottom-up synthesis and said top-down characterization until constraints are satisfied.

16. The process according to claim 15, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.

17. A computer system for synthesizing an integrated circuit (IC) design from a RTL code description into a gate-level description, said system comprising:

means for generating a generic netlist from the RTL code description;

means for identifying hardware elements in the generic netlist;

means for determining key pins for the identified hardware elements in the generic netlist;

means for extracting design structure and design hierarchy from the generic netlist based on the identified hardware elements and the key pins;

means for synthesizing the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,

wherein said synthesis of the IC design includes;

applying bottom-up synthesis to modules and sub-modules of the IC design,

applying top-down characterization to modules and sub-modules of the IC design, and

repeating said bottom-up synthesis and said top-down characterization until constraints are satisfied.

18. The computer system according to claim 17, wherein I/O conditions and I/O constraints of the modules of the IC design are captured during the top-down characterization and are used to re-optimize the IC design during the bottom-up synthesis.