Method for fabricating a vertical transistor, and semiconductor memory cell having a trench capacitor and an associated vertical selection transistor
First Claim
1. A method for fabricating a vertical transistor, which comprises the steps of:
- providing a monocrystalline semiconductor substrate having at least one trench formed therein with a lower section and an upper section, at least the lower section of the trench being lined with a storage dielectric and filled with at least one conductive material;
forming an auxiliary insulation layer on the conductive material;
depositing an epitaxial semiconductor layer on uncovered sidewalls of the upper section of the trench;
removing the auxiliary insulation layer;
conformally depositing a nitride layer, the nitride layer being so thin that it only partially impairs a current flow;
filling the trench with a doped further conductive material for producing an electrical connection between the conductive material situated in the lower section and a lower partial section of the epitaxial semiconductor layer, the lower partial section of the epitaxial semiconductor layer being doped by indiffusion of dopants from the further conductive material to form a first doping region;
forming a gate dielectric on uncovered regions of the epitaxial semiconductor layer;
forming a gate electrode on the gate dielectric; and
forming a second doping region in an upper partial section of the epitaxial semiconductor layer.
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Accused Products
Abstract
A semiconductor memory is fabricated with a vertical transistor situated in an upper section of a trench above a trench capacitor. First, an auxiliary insulation layer is applied to the conductive material of an inner electrode or to a connecting material of the trench capacitor. The connecting material is situated on the inner electrode, so that, during an epitaxial deposition, semiconductor material grows only on the uncovered sidewalls in the upper section of the trench. A nitride layer, is deposited conformally and the residual cavity between the inner electrode and the epitaxial semiconductor layer is filled with a doped further conductive material. The nitride layer isolates the epitaxial semiconductor layer from the further conductive material, so that no crystal lattice defects can propagate from there into the epitaxial semiconductor layer. Dopants are outdiffused from the further conductive material into the epitaxial semiconductor layer to form a doping region.
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Citations
21 Claims
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1. A method for fabricating a vertical transistor, which comprises the steps of:
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providing a monocrystalline semiconductor substrate having at least one trench formed therein with a lower section and an upper section, at least the lower section of the trench being lined with a storage dielectric and filled with at least one conductive material;
forming an auxiliary insulation layer on the conductive material;
depositing an epitaxial semiconductor layer on uncovered sidewalls of the upper section of the trench;
removing the auxiliary insulation layer;
conformally depositing a nitride layer, the nitride layer being so thin that it only partially impairs a current flow;
filling the trench with a doped further conductive material for producing an electrical connection between the conductive material situated in the lower section and a lower partial section of the epitaxial semiconductor layer, the lower partial section of the epitaxial semiconductor layer being doped by indiffusion of dopants from the further conductive material to form a first doping region;
forming a gate dielectric on uncovered regions of the epitaxial semiconductor layer;
forming a gate electrode on the gate dielectric; and
forming a second doping region in an upper partial section of the epitaxial semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A semiconductor memory cell, comprising:
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a monocrystalline semiconductor substrate having a trench formed therein with an upper section, a lower section, and sidewalls;
a trench capacitor disposed in said lower section, said trench capacitor having an inner electrode formed from a conductive material;
an epitaxial semiconductor layer disposed on said sidewalls of said upper section of said trench and having a lower partial section, an upper partial section, and a lower edge;
a vertical transistor disposed in said upper section of said trench and formed completely in said epitaxial semiconductor layer, said vertical transistor having a first doping region formed in said lower partial section of said epitaxial semiconductor layer and a second doping region formed in said upper partial section;
a storage dielectric lining said sidewalls of said lower section and having an upper edge, said lower edge of said epitaxial semiconductor layer extending at least as far as said upper edge of said storage dielectric;
an insulation collar disposed in a transition region between said lower section and said upper section, said insulation collar covering said storage dielectric;
a further conductive material electrically connecting said inner electrode of said trench capacitor to said first doping region of said vertical transistor; and
a nitride layer disposed at least between said further conductive material and said epitaxial semiconductor layer, said nitride layer having a thickness dimensioned to only partially impair a current flow. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification