Method of fabricating a high-voltage transistor with a multi-layered extended drain structure

• US 6,838,346 B2
• Filed: 11/25/2003
• Issued: 01/04/2005
• Est. Priority Date: 09/07/2001
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Disney, Donald Ray
• Primary Examiner(s): Nhu, David
• Application Number:
  US10/722,792
• Publication Number:
  US 20040082122A1
• Time in Patent Office: 406 Days
• Field of Search: 438/270, 438/197, 438/309, 438/311, 438/316, 438/414, 438/529, 438/589, 438/914
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: Y10S 438/925 Fluid growth doping control, e.g. delta doping

Abstract

A method for fabricating a high-voltage transistor with an extended drain region includes forming an epitaxial layer on a substrate, the epitaxal layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used o interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Claims

1. A method for fabricating an extended drain region of a high-voltage transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer being of first conductivity type and having a top surface;

etching the epitaxial layer to form first and second spaced-apart trenches that define a mesa with first and second sidewall portions;

forming a dielectric layer in each of the trenches, the dielectric layer partially filling each of the trenches and covering the first and second sidewall portions;

filling a remaining portion of the trenches with a conductive material to form first and second field plate members in the first and second trenches, respectively, each of the field plate members being insulated from the substrate and the epitaxial layer.

2. The method of claim 1 further comprising:

forming a source region of the first conductivity type at the top surface of the epitaxial layer, the extended drain region being defined between the source region and the substrate.

3. The method of claim 2 further comprising:

forming a source electrode connected to the source region and a drain electrode connected to the substrate.

4. The method of claim 1 wherein the dielectric layer an the field plate members are formed with a reduced spacing between the field plate members and the epitaxial layer near the top surface of the epitaxial layer as compared to near the substrate.

5. The method of claim 1 wherein the first conductivity type is n-type.

6. A method for fabricating an extended drain region of a power transistor comprising:

forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type;

etching the epitaxial layer to define a mesa having first and second sidewall portions and a top surface;

forming a dielectric material on the first and second sidewall portions;

forming first and second field plate members of a conductive material insulated from the first end second sidewall portions of the mesa, respectively, by the dielectric material.

7. The method of claim 6 further comprising:

forming a source region or the first conductivity type at the top surface, the extended drain region being defined between the source region and the substrate.

8. The method of claim 7 further comprising:

forming a source electrode connected to the source region and a drain electrode connected to the substrate.

9. The method of claim 6 wherein the dielectric material and the field plate members are formed with a reduced spacing between the field plate members and the mesa near the top surface as compared to near the substrate.

10. The method of claim 6 wherein the first conductivity type is n-type.

11. The method of claim 6 wherein the mesa is formed with a doping concentration that is lower near the top surface, as compared to near the substrate.

12. The method of claim 6 wherein the mesa is formed with a linearly graded doping profile.

13. The method of claim 6 wherein the dielectric material comprises silicon dioxide.

14. The method of claim 6 wherein the field plate members comprise doped polysilicon.

15. The method of claim 8 further comprising:

thinning the substrate prior to formation of the drain electrode.

16. The method of claim 6 wherein the is substrate is of the first conductivity type.