Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application

• US 6,838,725 B2
• Filed: 11/30/2000
• Issued: 01/04/2005
• Est. Priority Date: 07/06/1999
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Shui-Hung, Lin, Chrong-Jung
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): Dickey, Thomas L
• Application Number:
  US09/726,663
• Publication Number:
  US 20010000112A1
• Time in Patent Office: 1,496 Days
• Field of Search: 257/317, 257/320, 257314-316
• US Class Current: 257/317
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate

Abstract

A stacked-gate flash memory cell is provided having step-shaped poly-gates with increased overlap area between them in order to increase the coupling ratio and hence the program speed of the cell. The floating gate is first formed with a step and the intergate dielectric is conformally shaped thereon followed by the forming of the control gate thereon. The increase in the-overlap area can be achieved by forming gates with multiply connected surfaces of different shapes.

Claims

1. A stacked-gate flash memory cell having a floating Poly-Si gate with multiply connected surfaces of individual shapes comprising:

a semiconductor substrate having an active area;

a floating Poly-Si gate with a bottom surface and a multiply connected top surface;

said bottom surface being flat and overlying said active area;

said multiply connected top surface overlying said bottom surface;

said multiply connected top surface being defined by multiple regions of individual cross-sectional shapes, wherein the area of said multiply connected top surface overlying said active area is greater than the area of said bottom surface;

wherein said individual cross-sectional shapes are selected from a group consisting of rectangular, trapezoidal and triangular shapes;

a conformal inter-poly dielectric layer replicating said individual cross-sectional shapes over said floating Poly-Si gate; and

a conformal Poly-Si control gate replicating said individual cross-sectional shapes over said inter-poly dielectric layer;

wherein said regions of individual cross-sectional shapes have a depth between about 900 to 1000 Å

.

2. The stacked-gate flash memory cell of claim 1, wherein said inter-poly dielectric layer is oxide-nitride-oxide having a thickness between about 150 to 250 Å

.

3. The stacked-gate flash memory cell of claim 1, wherein said Poly-Si control gate has a thickness between about 1500 Å

to 2000 Å

.

4. The stacked-gate flash memory cell of claim 1, wherein said floating Poly-Si gate has a thickness between about 1900 Å

to 2100 Å

.