Semiconductor device and method for manufacturing the same

• US 6,838,732 B2
• Filed: 10/09/2001
• Issued: 01/04/2005
• Est. Priority Date: 04/06/2001
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Igarashi, Motoshige, Amishiro, Hiroyuki
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US09/971,958
• Publication Number:
  US 20020145156A1
• Time in Patent Office: 1,183 Days
• Field of Search: 257/288, 257/344, 257/346, 257/389, 438/303, 438/304
• US Class Current: 257/344
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

To provide a semiconductor device with reduced parasitic capacity in the vicinity of gate electrodes, and a method for manufacturing such a semiconductor device. The semiconductor device comprises a gate electrode formed on a silicon semiconductor substrate 1 through a gate oxide film, and a pair of impurity diffusion layers formed on the surface region of the silicon semiconductor substrate at both sides of the gate electrode. A silicon nitride film acting as a sidewall spacer is formed so as to cover the sidewall of the gate electrode, and the silicon nitride film is allowed to extend to the surface of the silicon semiconductor substrate 1 in the vicinity of the gate electrode in a substantially L-shaped profile.

Claims

1. A semiconductor device, comprising:

a gate electrode formed on a semiconductor substrate through a gate insulating film;

a pair of impurity diffusion layers formed on the surface region of said semiconductor substrate at both sides of said gate electrode;

a first insulating film formed so as to cover the sidewalls of said gate electrode, and to extend to the surface area of a specific range of said semiconductor substrate only in the vicinity of said gate electrode;

a second insulating film that covers said first insulating film and said semiconductor substrate including said gate electrode, and functions as an etch-stopper film, wherein said first insulating film is formed with a substantially uniform thickness, and

the thickness of said second insulating film on the sidewall of said gate electrode is smaller than the thickness of said second insulating film on the top surface of said gate electrode, and the thickness of said second insulating film on the sidewall of said gate electrode is smaller than the thickness of said second insulating film on the surface of said semiconductor substrate.

2. The semiconductor device according to claim 1, wherein the lateral length of said first insulating film is twice the thickness of said first insulating film or more at the side of said gate electrode.

3. The semiconductor device according to claim 1, further comprising an interlayer insulating film formed between gate electrodes adjacent to each other, and a hollow region is formed in said interlayer insulating film between said gate electrodes.

4. The semiconductor device according to claim 1, further comprising a low-resistance film on the side of said gate electrode.

5. The semiconductor device according to claim 1 further comprising an interlayer insulating film formed between said gate electrodes adjacent to each other, and a film that has a low specific inductive capacity at least lower than the specific inductive capacity of a silicon oxide film, said film being formed on said interlayer insulating film and said gate electrode.

6. The semiconductor device according to claim 1 further comprising a contact electrode connected to said gate electrode on said gate electrode, and connected to one of said impurity diffusion layers.

7. The semiconductor device according to claim 1, wherein said first insulating film is formed with a dual-layer film or a multi-layer film.

8. A semiconductor device, comprising:

a gate electrode formed on a semiconductor substrate through a gate insulating film;

a pair of impurity diffusion layers formed on the surface region of said semiconductor substrate at both sides of said gate electrode; and

a first insulating film formed so as to cover the sidewalls of said gate electrode, and to extend to the surface area of a specific range of said semiconductor substrate only in the vicinity of said gate electrode;

a second insulating film that covers said first insulating film and said semiconductor substrate including said gate electrode, and functions as an etch-stopper film, wherein said first insulating film is formed with a substantially uniform thickness, and

the thickness of said second insulating film on the top surface of said gate electrode is greater than the thickness of said second insulating film on the surface of said semiconductor substrate.

9. The semiconductor device according to claim 8, wherein said first insulating film is formed with a dual-layer film or a multi-layer film.

10. A semiconductor device, comprising:

a gate electrode formed on a semiconductor substrate through a gate insulating film;

a pair of impurity diffusion layers formed on the surface region of said semiconductor substrate at both sides of said gate electrode; and

a first insulating film formed so as to cover the sidewalls of said gate electrode, and to extend to the surface area of a specific range of said semiconductor substrate only in the vicinity of said gate electrode, wherein said first insulating film is formed with a substantially uniform thickness, and

the sum of the thickness of said first insulating film and the thickness of a second insulating film on the sidewall of said gate electrode is substantially equal to the lateral length of said first insulating film at the side of said gate electrode.

11. The semiconductor device according to claim 10, wherein said first insulating film is formed with a dual-layer film or a multi-layer film.