Trench FET with non overlapping poly and remote contact therefor

• US 6,838,735 B1
• Filed: 02/24/2000
• Issued: 01/04/2005
• Est. Priority Date: 02/24/2000
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Pavier, Mark, Kinzer, Daniel M., Sodhi, Ritu
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Sefer, Ahmed N.
• Application Number:
  US09/512,497
• Time in Patent Office: 1,776 Days
• Field of Search: 257327-332, 257339-342, 257/365, 257270-271, 257587-589
• US Class Current: 257/365
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOSFET has a plurality of spaced rows of parallel coextensive trenches. The trenches are lined with a gate oxide and are filled with conductive polysilicon. Spaced narrow polysilicon strips overlie the silicon surface and connects adjacent trenches to one another. The source contact is made at a location remote from the trenches and between the rows of trenches. The trenches are 1.8 microns deep, are 0.6 microns wide and are spaced by about 0.6 microns or greater. The device has a very low figure of merit and is useful especially in low voltage circuits.

Claims

1. A MOSgated device comprising:

a semiconductor body of a first conductivity type;

a channel region of a second conductivity type formed in said semiconductor body;

a conductive region of said first conductivity type formed in said semiconductor body and extending from a first major surface of said semiconductor body to at least said channel region;

a plurality of spaced trenches extending into said semiconductor body below said channel region, each of said trenches being adjacent a mesa and each terminating at a contact region in said semiconductor body, said channel region and said conductive region extending into said contact region, and said conductive region uninterruptedly extending between each two adjacently disposed trenches;

a gate insulation layer dispose over the sidewalls and bottom of each of said trenches;

a gate electrode formed in each of said trenches over said gate insulation layer;

at least one conductive strip extending transverse to and over each of said trenches and electrically connected to each of said gate electrodes;

said conductive strip being narrower than the length of said gate electrodes such that it makes contact only with a portion of each of said gate electrodes; and

a remote contact formed over at least said contact region and in electrical contact with at least said conductive region.

2. A MOSgated device according to claim 1, wherein said remote contact extends through said conductive region to make contact with said channel region below said conductive region.

3. A MOSgated device according to claim 1, wherein said conductive region is a source region.

4. A MOSgated device according to claim 1, wherein said gate electrode comprises conductive polysilicon.

5. A MOSgated device according to claim 1, wherein said gate insulation layer comprises an oxide.

6. A MOSgated device according to claim 1, wherein said semiconductor body is an epitaxial silicon layer formed over a silicon substrate of the same conductivity and further comprising a second contact in electrical contact with said substrate.

7. A MOSgated device according to claim 6, wherein said second contact is a drain contact.

8. A MOSgated device according to claim 1, wherein said remote contact is a source contact.

9. A MOSgated device according to claim 1, wherein said plurality of spaced trenches are parallel to one another and are coextensive with one another.

10. A MOSgated device according to claim 1, wherein said plurality of spaced trenches are formed in a plurality of spaced rows and are parallel to one another and are coextensive with one another within each row.

11. A MOSgated device according to claim 1, wherein said trenches have a depth of about 1.8 microns.

12. A MOSgated device according to claim 1, wherein said trenches extend to about 0.2 to 0.25 microns below said channel region.

13. A MOSgated device according to claim 1, wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.

14. A MOSgated device according to claim 1, wherein said gate insulation is an oxide layer having a thickness greater than about 200 Å

and which fully covers the interior of each of said trenches.

15. A MOSgated device comprising:

an epitaxial silicon body of a first conductivity type;

a channel region of a second conductivity type formed in said epitaxial silicon body;

a source region of said first conductivity type formed in said epitaxial silicon body and extending from a first major surface of said silicon body to at least said channel region;

a plurality of spaced trenches extending into said silicon body below said channel region, each of said trenches being adjacent a mesa and each terminating at a source contact region in said silicon body, said channel region and said source region extending into said source contact region, and said source region uninterruptedly extending between each two adjacently disposed trenches;

a gate oxide layer dispose over the sidewalls and bottom of each of said trenches;

a polysilicon gate electrode formed in each of said trenches over said gate oxide layer;

at least one conductive strip extending transverse to and over each of said trenches and electrically connected to each of said polysilicon gate electrodes;

said conductive strip being narrower than the length of said polysilicon gate electrode such that it makes contact only with a portion of each of said polysilicon gate electrodes; and

a remote source contact formed over at least said source contact region and in electrical contact with at least said source region.

16. A MOSgated device according to claim 15, wherein said remote source contact extends through said source region to make contact with said channel region below said source region.

17. A MOSgated device according to claim 15, further comprising a silicon substrate and a drain contact in electrical connection with said substrate, said epitaxially silicon substrate being formed over said substrate.

18. A MOSgated device according to claim 15, wherein said plurality of spaced trenches are parallel to one another and are coextensive with one another.

19. A MOSgated device according to claim 15, wherein said plurality of spaced trenches are formed in a plurality of spaced rows and are parallel to one another and are coextensive with one another within each row.

20. A MOSgated device according to claim 15, wherein said trenches have a depth of about 1.8 microns.

21. A MOSgated device according to claim 15, wherein said trenches extend to about 0.2 to 0.25 microns below said channel region.

22. A MOSgated device according to claim 15, wherein said trenches have a width of about 0.6 microns and a spacing of about 0.6 microns or greater.