Circuit device with at least partial packaging and method for forming

• US 6,838,776 B2
• Filed: 04/18/2003
• Issued: 01/04/2005
• Est. Priority Date: 04/18/2003
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Leal, George R., Wenzel, Robert J., Sawyer, Brian D., Wontor, David G., Prack, Edward R., Mangrum, Marc Alan, Zhao, Jie-Hua
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US10/418,763
• Publication Number:
  US 20040207068A1
• Time in Patent Office: 627 Days
• Field of Search: 257/783, 257/787, 257/723, 438/25, 438/26, 438/105, 438/106, 438/110
• US Class Current: 257/783
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Claims

1. A device with at least partial packaging, comprising:

an electrically conductive layer having a first surface and a second surface, opposite the first surface;

a circuit device overlying the electrically conductive layer, the circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry, and the first surface of the circuit device is between the second surface of the circuit device and the first surface of the electrically conductive layer; and

an encapsulant layer overlying the first surface of the electrically conductive layer,

wherein the electrically conductive layer comprises at least one opening that exposes at least a portion of the first surface of the circuit device.

2. The device of claim 1, further comprising an adhesive layer between the first surface of the circuit device and the first surface of the electrically conductive layer.

3. The device of claim 1, wherein the encapsulant layer overlies the second surface of the circuit device.

4. The device of claim 1, wherein at least two portions of the electrically conductive layer extend through the encapsulant layer, and wherein the device fiber comprises a second circuit device having a first terminal coupled to one of the at least two portions of the electrically conductive layer and a second terminal coupled to another one of the at least two portions of the electrically conductive layer.

5. The device of claim 4, wherein the second circuit device is selected from a group consisting of a passive device, an optical device, an active device, a semiconductor device, an antennae, and a micro-electromechanical system (MEMS) device.

6. The device of claim 1, wherein the electrically conductive layer comprises a lead frame.

7. The device of claim 2, wherein the adhesive layer is removed.

8. The device of claim 1, wherein the encapsulant layer comprises an electrically conductive material.

9. The device of claim 1, wherein the encapsulant layer comprises an electrically conductive portion overlying the second surface of the circuit device.

10. The device of claim 1, further comprising a second circuit device having a first terminal and a second terminal, wherein the first terminal is coupled to a first physically separate portion of the electrically conductive layer and the second terminal is coupled to a second physically separate portion of the electrically conductive layer.

11. The device of claim 10, wherein the encapsulant layer overlies the second circuit device.

12. The device of claim 1, wherein the electrically conductive layer comprises at least two portions electrically isolated from each other.

13. The device of claim 12, wherein one of the at least two portions comprises a first voltage reference plane.

14. The device of claim 13, wherein another one of the at least two portions comprises a second voltage reference plane.

15. The device of claim 14, further comprising a second circuit device having a first terminal coupled to the first voltage reference plane and a second terminal coupled to the second voltage reference plane.

16. The device of claim 1, further comprising an interconnect layer overlying the second surface of the electrically conductive layer.

17. The device of claim 16, wherein the interconnect layer comprises a plurality of interconnect levels.

18. The device of claim 16, further comprising a compliant layer overlying the interconnect layer.

19. The device of claim 18, wherein the compliant layer comprises a plurality of electrically conductive vias coupled to the interconnect layer.

20. The device of claim 19, further comprising a plurality of conductive balls coupled to the electrically conductive vias.

21. The device of claim 16, wherein the interconnect layer comprises a same material as the encapsulant layer.

22. The device of claim 21, wherein the same material is a material selected from a group consisting of liquid crystal polymer and PPS.

23. The device of claim 1, further comprising a plurality of circuit devices overlying the first surface of the electrically conductive layer, each of the plurality of circuit devices having a first surface comprising active circuitry and a second surface opposite the first surface, wherein the first surfaces of each of the plurality of the circuit devices is between the second surfaces of each of the plurality of circuit devices and the first surface of the electrically conductive layer.

24. The device of claim 23, wherein the encapsulant layer overlies at least a portion of the second surfaces of the plurality of circuit devices.

25. The device of claim 24, wherein the encapsulant layer comprises an electrically conductive material.

26. The device of claim 1, wherein the electrically conductive layer comprises a plurality of interconnect layers.

27. The device of claim 1, wherein the electrically conductive layer comprises a reference voltage plane.

28. The device of claim 27 wherein the reference voltage plane comprises a ground plane.

29. A device with at least partial packaging, comprising:

an electrically conductive layer having a first surface and a second surface, opposite the first surface;

an adhesive layer overlying and in physical contact with the first surface of the electrically conductive layer;

a circuit device overlying the adhesive layer, the circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry and is in physical contact with the adhesive layer; and

an encapsulant layer overlying the first surface of the electrically conductive layer.

30. The device of claim 29, wherein the encapsulant layer overlies the second surface of the circuit device.

31. The device of claim 29, wherein the electrically conductive layer comprises at least one opening that exposes at least a portion of the first surface of the circuit device.

32. The device of claim 29, wherein the encapsulant layer comprises an electrically conductive material.

33. The device of claim 29, wherein the encapsulant layer comprises an electrically conductive portion overlying the second surface of the second device.

34. The device of claim 29, further comprising a second circuit device having a first terminal and a second terminal, wherein the first terminal is coupled to a first physically separate portion of the electrically conductive layer and the second terminal is coupled to a second physically separate portion of the electrically conductive layer.

35. The device of claim 34, wherein the encapsulant layer overlies the second circuit device.

36. The device of claim 29, wherein the electrically conductive layer comprises a ground reference plane.

37. A method for forming a device with at least partial packaging, comprising:

providing an electrically conductive layer having a first surface and a second surface opposite the first surface,

positioning a circuit device over the electrically conductive layer, the circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry and the first surface of the circuit device is between the second surface of the circuit device and the first surface of the electrically conductive layer,

forming an encapsulant layer overlying the first surface of the electrically conductive layer; and

providing at least one opening in the electrically conductive layer, wherein the at least one opening permits electrical contact to the circuit device.

38. The method of claim 37, wherein positioning the circuit device comprises adhering the first surface of the circuit device to the electrically conductive layer.

39. The method of claim 37, wherein forming the encapsulant layer comprises forming the encapsulant layer overlying circuit device.

40. A device with at least partial packaging, comprising:

an electrically conductive layer having a first surface and a second surface, opposite the first surface;

a circuit device overlying the electrically conductive layer, the circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry, and the first surface of the circuit device is between the second surface of the circuit device and the first surface of the electrically conductive layer;

an encapsulant layer overlying the first surface of the electrically conductive layer, and

an adhesive layer between the first surface of the circuit device and the first surface of the electrically conductive layer.

41. The device of claim 40, wherein the adhesive layer comprises tape.

42. The device of claim 40, wherein the adhesive layer comprises epoxy.

43. The device of claim 40, wherein the adhesive layer is removed.