Semiconductor device and method of manufacturing the same

• US 6,838,777 B2
• Filed: 08/27/2003
• Issued: 01/04/2005
• Est. Priority Date: 04/17/2003
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Igarashi, Motoshige
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/648,223
• Publication Number:
  US 20040207098A1
• Time in Patent Office: 496 Days
• Field of Search: 257/900
• US Class Current: 257/339
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Gate electrodes (3) are formed on a semiconductor substrate (1), each with a gate insulating film (2) interposed therebetween. A pair of offset spacers (4) are respectively formed on opposite side faces of each of the gate insulating film (2) and the gate electrodes (3). Diffusion layers (5) are formed in the semiconductor substrate (1) on opposite sides of a portion of the semiconductor substrate (1) immediately under each of the gate electrodes (3), by ion implantation. While the gate electrodes (3) have various configurations such as a gate electrode having a rectangular section, an upwardly tapered gate electrode and a downwardly tapered gate electrode, respective configurations of the offset spacers (4) are adjusted so that lengths each obtained by adding the gate length of the gate electrode (3), which gate length extends on an interface between the gate insulating film (2) and the gate electrode (3), to a width of the pair of the offset spacers (4), which width extends on an interface between the offset spacers (4) and the semiconductor substrate (1), are substantially uniform.

Claims

1. A semiconductor device comprising;

a plurality of gate electrode structures formed on a semiconductor substrate, each of which comprises;

a gate insulating film formed on said semiconductor substrate;

a gate electrode formed on said gate insulating film; and

an offset spacer formed on a side face of said gate electrode;

wherein respective lengths of said plurality of gate electrode structures are substantially uniform with one another, each of said lengths being defined as a sum of a gate length extending on an interface between said gate insulating film and said gate electrodes, and a width of said offset spacer extending on an interface between said offset spacer and said semiconductor substrate, and

said plurality of gate electrode structures include a first gate electrode having a rectangular section, a second gate electrode having a upwardly tapered section, and a third gate electrode having a downwardly tapered section.

2. The semiconductor device according to claim 1,

wherein a pair of shallow source/drain regions and a pair of deep source/drain regions are formed to form a MOSFET, said regions in each of said pairs being formed in said semiconductor substrate on opposite sides of a portion of said semiconductor substrate immediately under said gate electrode.