Low power analog to digital converter

• US 6,839,015 B1
• Filed: 12/06/2002
• Issued: 01/04/2005
• Est. Priority Date: 12/06/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat, Aram, Farbod
• Primary Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US10/313,369
• Time in Patent Office: 760 Days
• Field of Search: 341/161, 341/172, 341/155, 341/122, 341/142, 341/143, 341/135, 330/254, 331/17, 323/282, 327/541
• US Class Current: 341/161
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/168 and delivering the same number of bits
• CPC Class Codes: H03M 1/442 using switched capacitors

Abstract

An analog to digital converter includes a first charging circuit that samples an input voltage during a charging phase. A first opamp has an input that communicates with the first charging circuit during an integrating phase. A first current source selectively generates a first bias current for the first opamp during the charging phase and a second bias current that is not equal to the first bias current during the integrating phase. The first bias current is less than the second bias current. The first current source can be a variable current source that selectively provides the first and second bias currents during the charging and integrating phases, respectively. Alternately, the first current source can include two current sources. Only one of the two current sources is connected to the first opamp during the integrating phase.

Claims

1. An analog to digital converter, comprising:

a first charging circuit that samples an input voltage during a charging phase;

a first opamp having an input that communicates with said first charging circuit during an integrating phase;

a first current source that selectively generates a first bias current for said first opamp during said charging phase and a second bias current that is not equal to said first bias current during said integrating phase;

a second charging circuit that is charged by an output of said first opamp during a second charging phase;

a second opamp having an input that communicates with said second charging circuit during a second integrating phase; and

a second current source that selectively generates said first bias current for said second opamp during said second charging phase and said second bias current for said second opamp during said second integrating phase.

2. The analog to digital converter of claim 1 wherein said first and second current sources comprise:

a current source;

a switching device that communicates with said current source, that selectively connects said current source to said first opamp as said current source is disconnected from said second opamp to provide said second bias current to said first opamp during said integrating phase of said first opamp.

3. The analog to digital converter of claim 2 wherein said current source comprises a current mirror.

4. The analog to digital converter of claim 3 wherein said switching device comprises first and second switches that communicate with said current mirror.

5. The analog to digital converter of claim 2 wherein said switching device selectively disconnects said current source from said first opamp as said current source is connected to said second opamp to provide said second bias current to said second opamp during said integrating phase of said second opamp.

6. The analog to digital converter of claim 1 wherein said first bias current is less than said second bias current.

7. The analog to digital converter of claim 1 wherein said first bias current is zero and said second bias current is greater than zero.

8. The analog to digital converter of claim 1 further comprising a first switching circuit that communicates with said input of said first opamp, said first charging circuit and said first current source, charges said first charging circuit using said input voltage and operates said first current source to supply said first bias current to said first opamp during said charging phase, and that isolates said first charging circuit from said input voltage and operates said first current source to supply said second bias current to said first opamp during said integrating phase.

9. The analog to digital converter of claim 1 wherein said first current source is a variable current source that selectively provides said first and second bias currents during said charging and integrating phases, respectively.

10. The analog to digital converter of claim 1 wherein said first current source includes two current sources, and wherein only one of said two current sources is connected to said first opamp during said integrating phase.

11. The analog to digital converter of claim 1 further comprising a second switching circuit that communicates with said input of said second opamp, said second charging circuit and said second current source, charges said second charging circuit using said output of said second opamp, and operates said second current source to supply said first bias current to said second opamp during said second charging phase, and that isolates said second charging circuit from said output of said first opamp and operates said second current source to supply said second bias current to said second opamp during said second integrating phase.

12. The analog to digital converter of claim 1 wherein said first charging circuit includes at least one capacitor.

13. The analog to digital converter of claim 1 wherein said charging phase and said second integrating phase occur at the same time and said integrating phase and said second charging phase occur at the same time.

14. A multi-stage pipelined analog to digital converter, comprising:

a first stage including first charging circuit that samples an input voltage during a charging phase, a first opamp having an input that communicates with said first charging circuit during an integrating phase, a first current source that selectively generates a first bias current for said first opamp during said charging phase and a second bias current that is not equal to said first bias current during said integrating phase, and a first switching circuit that communicates with said input of said first opamp, said first charging circuit and said first current source, charges said first charging circuit using said input voltage, and operates said first current source to supply said first bias current to said first opamp during said charging phase, and that isolates said first charging circuit from said input voltage and operates said first current source to supply said second bias current to said first opamp during said integrating phase; and

a second stage including a second charging circuit that samples an output of said first opamp during a second charging phase, a second opamp having an input that communicates with said second charging circuit during a second integrating phase, a second current source that selectively generates said first bias current for said second opamp during said second charging phase and said second bias current for said second opamp during said second integrating phase, and a second switching circuit that communicates with said input of said second opamp, said second charging circuit and said second current source, charges said second charging circuit using said output of said first opamp, and operates said second current source to supply said first bias current to said second opamp during said second charging phase, and that isolates said second charging circuit from said output of said first opamp and operates said second current source to supply said second bias current to said second opamp during said second integrating phase.

15. The analog to digital converter of claim 14 wherein said first and second current sources comprise:

a current source;

a switching device that communicates with said current source, that selectively connects said current source to said first opamp as said current source is disconnected from said second opamp to provide said second bias current to said first opamp during said integrating phase of said first opamp.

16. The analog to digital converter of claim 15 wherein said current source comprises a current mirror.

17. The analog to digital converter of claim 16 wherein said switching device comprises first and second switches that communicate with said current mirror.

18. The analog to digital converter of claim 15 wherein said switching device selectively disconnects said current source from said first opamp as said current source is connected to said second opamp to provide said second bias current to said second opamp during said integrating phase of said second opamp.

19. The multi-stage pipelined analog to digital converter of claim 14 wherein said first bias current is less than said second bias current.

20. The multi-stage pipelined analog to digital converter of claim 14 wherein said first bias current is zero and said second bias current is greater than zero.

21. The multi-stage pipelined analog to digital converter of claim 14 wherein said charging phase and said second integrating phase occur at the same time and said integrating phase and said second charging phase occur at the same time.

22. The multi-stage pipelined analog to digital converter of claim 14 wherein said first and second charging circuits include at least one capacitor.

23. An analog to digital converter, comprising:

first charging means for sampling an input voltage during a charging phase;

first integrating means for communicating with said first charging means during an integrating phase; and

first current means for selectively generating a first bias current for said first integrating means during said charging phase and a second bias current that is not equal to said first bias current during said integrating phase;

second charging means for sampling an output of said first integrating means during a second charging phase;

second integrating means for communicating with said second charging means during a second integrating phase; and

second current means for selectively generating said first bias current for said second integrating means during said second charging phase and said second bias current during said second integrating phase.

24. The analog to digital converter of claim 23 wherein said first and second current means comprise:

current means for providing current;

switching means that communicates with said current means, that selectively connects said current means to said first integrating means as said current means is disconnected from said second integrating means to provide said second bias current to said first integrating means during said integrating phase of said first integrating means.

25. The analog to digital converter of claim 24 wherein said current means comprises a current mirror.

26. The analog to digital converter of claim 25 wherein said switching means comprises first and second switches that communicate with said current mirror.

27. The analog to digital converter of claim 24 wherein said switching means selectively disconnects said current means from said first integrating means as said current source is connected to said second integrating means to provide said second bias current to said second integrating means during said integrating phase of said second integrating means.

28. The analog to digital converter of claim 23 wherein said first bias current is less than said second bias current.

29. The analog to digital converter of claim 23 wherein said first bias current is zero and said second bias current is greater than zero.

30. The analog to digital converter of claim 23 further comprising first switching means that communicates with said first integrating means, said first charging means and said first current means, for charging said first charging means using said input voltage and operating said first current means to supply said first bias current to said first integrating means during said charging phase, and for isolating said first charging means from said input voltage and operating said first current means to supply said second bias current to said first integrating means during said integrating phase.

31. The analog to digital converter of claim 23 wherein said first current means is a variable current source that selectively provides said first and second bias currents during said charging and integrating phases, respectively.

32. The analog to digital converter of claim 23 wherein said first current means includes two current sources, and wherein only one of said two current sources is connected to said first opamp during said integrating phase.

33. The analog to digital converter of claim 23 further comprising second switching means that communicates with said second integrating means, said second charging means and said second current means, for charging said second charging means using said output of said second integrating means and operating said second current means to supply said first bias current to said second integrating means during said second charging phase, and for isolating said second charging means from said output of said first integrating means and operating said second current means to supply said second bias current to said second integrating means during said second integrating phase.

34. The analog to digital converter of claim 23 wherein said first charging means includes at least one capacitor.

35. The analog to digital converter of claim 23 wherein said charging phase and said second integrating phase occur at the same time and said integrating phase and said second charging phase occur at the same time.

36. A multi-stage pipelined analog to digital converter, comprising:

a first stage including first charging means for sampling an input voltage during a charging phase, first integrating means for communicating with said first charging means during an integrating phase, first current means for selectively generating a first bias current for said first integrating means during said charging phase and a second bias current that is not equal to said first bias current during said integrating phase, and a first switching means that communicates with said first integrating means, said first charging means and said first current means, for charging said first charging means using said input voltage and operating said first current means to supply said first bias current to said first integrating means during said charging phase, and for isolating said first charging means from said input voltage and operating said first current means to supply said second bias current to said first integrating means during said integrating phase; and

a second stage including second charging means for sampling an output of said first integrating means during a second charging phase, second integrating means for communicating with said second charging means during a second integrating phase, second current means for selectively generating said first bias current for said second integrating means during said second charging phase and said second bias current for said second integrating means during said second integrating phase, and second switching means that communicates with said input of said second integrating means, said second charging means and said second current means, for charging said second charging means using said output of said first integrating means and operating said second current means to supply said first bias current to said second integrating means during said second charging phase; and

for isolating said second charging means from said output of said first integrating means and operating said second current means to supply said second bias current to said second integrating means during said second integrating phase.

37. The analog to digital converter of claim 36 wherein said first and second current means comprise:

current means for providing current;

switching means that communicates with said current means, that selectively connects said current means to said first integrating means as said current means is disconnected from said second integrating means to provide said second bias current to said first integrating means during said integrating phase of said first integrating means.

38. The analog to digital converter of claim 37 wherein said current means comprises a current mirror.

39. The analog to digital converter of claim 38 wherein said switching means comprises first and second switches that communicate with said current mirror.

40. The analog to digital converter of claim 37 wherein said switching means selectively disconnects said current means from said first integrating means as said current source is connected to said second integrating means to provide said second bias current to said second integrating means during said integrating phase of said second integrating means.

41. The multi-stage pipelined analog to digital converter of claim 36 wherein said first bias current is less than said second bias current.

42. The multi-stage pipelined analog to digital converter of claim 36 wherein said first bias current is zero and said second bias current is greater than zero.

43. The multi-stage pipelined analog to digital converter of claim 36 wherein said charging phase and said second integrating phase occur at the same time and said integrating phase and said second charging phase occur at the same time.

44. The multi-stage pipelined analog to digital converter of claim 36 wherein said first and second charging means include at least one capacitor.

45. A method for operating an analog to digital converter, comprising:

storing an input voltage during a charging phase;

integrating said stored input voltage during an integrating phase using an opamp; and

selectively generating a first bias current for said opamp during said charging phase and a second bias current that is not equal to said first bias current during said integrating phase;

storing an output of said first opamp during a second charging phase;

integrating said stored output of said first opamp during a second integrating phase; and

selectively generating said first bias current for said second opamp during said second charging phase and said second bias current for said second opamp during said second integrating phase.

46. The method of claim 45 further comprising selectively connecting a current source to a first opamp as said current source is disconnected from a second opamp to provide said second bias current to said first opamp during said integrating phase of said first opamp.

47. The method of claim 46 further comprising selectively disconnecting said current source from said first opamp as said current source is connected to said second opamp to provide said second bias current to said second opamp during said integrating phase of said second opamp.

48. The method of claim 46 wherein said current source comprises a current mirror.

49. The method of claim 45 wherein said first bias current is less than said second bias current.

50. The method of claim 45 wherein said first bias current is zero and said second bias current is greater than zero.

51. The method of claim 45 wherein said first and second bias currents are supplied by a variable current source during said charging and integrating phases, respectively.

52. The method of claim 45 wherein an output of one of two current sources is connected to said first opamp during said integrating phase.

53. The method of claim 45 wherein said charging phase and said second integrating phase occur at the same time and said integrating phase and said second charging phase occur at the same time.