Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs
First Claim
1. A method of addressing a memory device having a high density operating mode and a low density operating mode, the method comprising:
- receiving a first set of row address bits and a specific row address bit;
storing the specific row address bit;
receiving a first set of column address bits and a specific column address bit;
determining the operating mode of the memory device;
in the high density operating mode, selecting the first set of column address bits and the specific column address bit;
in the low density operating mode, selecting the first set of column address bits and the specific row address bit; and
addressing a column of the memory device using the selected address bits.
1 Assignment
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Accused Products
Abstract
A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode. The SDRAM also includes circuitry for remapping one of the row address bits for use as a column address bit in the half density mode so that the SDRAM can interface with system adapted for conventional dual mode SDRAMs.
68 Citations
13 Claims
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1. A method of addressing a memory device having a high density operating mode and a low density operating mode, the method comprising:
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receiving a first set of row address bits and a specific row address bit;
storing the specific row address bit;
receiving a first set of column address bits and a specific column address bit;
determining the operating mode of the memory device;
in the high density operating mode, selecting the first set of column address bits and the specific column address bit;
in the low density operating mode, selecting the first set of column address bits and the specific row address bit; and
addressing a column of the memory device using the selected address bits. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of addressing an array of memory cells arranged in a matrix along first and second axes, the array of memory cells being addressed in either a high density operating mode and a low density operating mode, the method comprising:
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receiving a first set address bits and a second address bit;
receiving a third set of address bits and a fourth address bit;
determining the operating mode of the DRAM;
in the high density operating mode, addressing the array of memory cells along the first axis using the first set of address bits and the second address bit and addressing the array of memory cells along the second axis using the third set of address bits and the fourth address bits; and
in the low density operating mode, addressing the array of memory cells along the first axis using the first set of address bits and the fourth address bit, and addressing the array of memory cells along the second axis using the third set of address bits. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification