MAC/PHY interface

• US 6,839,345 B2
• Filed: 12/15/2000
• Issued: 01/04/2005
• Est. Priority Date: 12/17/1999
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lu, Xiaolin, Shaver, Donald P.
• Primary Examiner(s): Pezzlo, John
• Application Number:
  US09/737,722
• Publication Number:
  US 20020078247A1
• Time in Patent Office: 1,481 Days
• Field of Search: 370/282, 370/401, 370/364, 370/365, 370/419, 710/305
• US Class Current: 370/365
• CPC Class Codes: H04L 12/2838 Distribution of signals within a home automation network, e.g. involving splitting/multiplexing signals to/from different paths adaptations of television systems for transmission by electric cable for domestic distribution H04N7/106; hybrid transport H04L12/6418; home network arrangements specially adapted for distribution of digital video signals H04N7/24
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/321 Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04W 74/00 Wireless channel access

Abstract

The present invention provides a method, system and apparatus for managing data flow over an open system interconnection type network (10) which includes a physical layer (12) and a media access control layer (146). The invention implements a plurality of operating modules (315) each enabling a respective media access control layer operating function in which at least a portion of the operating modules are implemented in software. The invention further implements a host interface module (305) for communication between a host processor and the media access control layer, a physical layer interface module (310) for communication between the physical layer and media access control layer, and an inter-module programming interface for communications between respective operating modules. The physical layer interface includes an enhanced media independent interface in accordance with some embodiments of the present invention.

Claims

1. A system for interfacing in an open system interconnection type network, said system comprising:

a media access control layer configured to manage data flow over said open system interconnection type network;

a physical layer configured to code data for transmission to a medium;

an eight bit transmit data bus configured to enable data transfer from said media access control layer to said physical layer, wherein said eight bit transmit data bus is driven by said media access control layer;

an eight bit receive data bus configured to enable data transfer from said physical layer to said media access control layer, wherein said eight bit receive data bus is driven by said physical layer;

a transmit ON signal bus configured to indicate to said physical layer that a data frame is available on said eight bit transmit data bus and to indicate a request by said media access control layer for said physical layer to apply a backoff signal; and

a receive ON signal bus configured to indicate that to said media access layer valid data is available on said eight bit receive data bus and to indicate that a backoff signal request is received.

2. The system of claim 1, wherein said eight bit transmit data bus is further configured to enable direct memory access (DMA) from a digital signal processor (DSP), wherein said DSP implements a programmable digital signal processing function of said physical layer.

3. The system of claim 1, wherein said eight bit receive data bus is further configured to enable direct memory access (DMA) to a digital signal processor (DSP), wherein said DSP implements a programmable digital signal processing function of said physical layer.

4. The system of claim 1, wherein said media access control layer request said backoff signal upon detection of a collision condition.

5. The system of claim 1 further comprising a transmit HPNA mode signal bus configured to indicate that a HPNA 1.0 type data frame is available for transmission on said eight bit transmit data bus.

6. The system of claim 1 further comprising a receive HPNA mode signal bus configured to indicate that a HPNA 1.0 type data frame is available for transmission on said eight bit receive data bus.

7. The system of claim 1, wherein said backoff signal comprises a HPNA type backoff signal.

8. The system of claim 1 further comprising a register set configured for managing data signal exchange between said media access control layer and physical layer.

9. The system of claim 8, wherein a first portion of said register set is implemented in said media access control layer and a second portion of said register set is implemented in said physical layer.

10. The system of claim 1 further comprising:

a backoff signal slot ON data bus configured to indicate a start of a backoff signal slot;

a transmit enable data bus configured to indicate that a new data frame can be placed on said eight bit transmit data bus;

a reference clock sourced by said physical layer;

a carrier sense signal bus configured to indicate idle and non-idle conditions on transmit and receive mediums;

a collision detection signal bus configured to indicate a collision condition on said transmit and receive mediums;

a receive error signal data bus configured to indicate an error detection in a transmit data frame; and

a receive enable data bus configured to indicate placement of new data on said eight bit receive data bus.

11. A media interface for data exchange between a media access control layer and a physical layer in an open system interconnection layered type network, said media interface comprising:

an eight bit transmit data bus configured to enable data transfer from said media access control layer to said physical layer, wherein said eight bit transmit data bus is driven by said media access control layer;

an eight bit receive data bus configured to enable data transfer from said physical layer to said media access control layer, wherein said eight bit receive data bus is driven by said physical layer;

a transmit ON signal bus configured to indicate to said physical layer that a data frame is available on said eight bit transmit data bus and to indicate a request by said media access control layer for said physical layer to apply a backoff signal; and

a receive ON signal bus configured to indicate to said media access control layer that valid data is available on said eight bit receive data bus and to indicate that a backoff signal request is received.

12. The media interface of claim 11, wherein said eight bit transmit data bus is further configured to enable direct memory access (DMA) from a digital signal processor (DSP), wherein said DSP implements a programmable digital signal processing function of said physical layer.

13. The media interface of claim 11, wherein said eight bit receive data bus is further configured to enable direct memory access (DMA) to a digital signal processor (DSP), wherein said DSP implements a programmable digital signal processing function of said physical layer.

14. The media interface of claim 11, wherein said media access control layer request said backoff signal upon detection of a collision condition.

15. The media interface of claim 11 further comprising a transmit HPNA mode signal bus configured to indicate that a HPNA 1.0 type data frame is available for transmission on said eight bit transmit data bus.

16. The media interface of claim 11 further comprising a receive HPNA mode signal bus configured to indicate that a HPNA 1.0 type data frame is available for transmission on said eight bit receive data bus.

17. The media interface of claim 11, wherein said backoff signal comprises a HPNA type backoff signal.

18. The media interface of claim 11 further comprising a register set configured for managing data signal exchange between said media access control layer and physical layer.

19. The media interface of claim 18, wherein a first portion of said register set is implemented in said media access control layer and a second portion of said register set is implemented in said physical layer.

20. The media interface of claim 11 further comprising:

a backoff signal slot ON data bus configured to indicate a start of a backoff signal slot;

a transmit enable data bus configured to indicate that a new data frame can be placed on said eight bit transmit data bus;

a reference clock sourced by said physical layer;

a carrier sense signal bus configured to indicate idle and non-idle conditions on transmit and receive mediums;

a collision detection signal bus configured to indicate a collision condition on said transmit and receive mediums;

a receive error signal data bus configured to indicate an error detection in a transmit data frame; and

a receive enable data bus configured to indicate placement of new data on said eight bit receive data bus.