Digital quadrature demodulation and decimation without multipliers

• US 6,839,389 B2
• Filed: 03/13/2001
• Issued: 01/04/2005
• Est. Priority Date: 03/13/2000
• Status: Expired due to Fees

• Current Assignee: PRI Research & Development Corp.
• Original Assignee: PRI Research & Development Corp.
• Inventors: Mehrnia, Alireza, Shakeri, Kaveh
• Primary Examiner(s): Ha, Dac V.
• Application Number:
  US09/805,530
• Publication Number:
  US 20020025006A1
• Time in Patent Office: 1,393 Days
• Field of Search: 375/260, 375/324, 375/328, 375/340, 375/351, 329/304, 329/305, 329/310, 329/363, 329/364
• US Class Current: 375/328
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: H04B 1/707 using direct sequence modulation

Abstract

One embodiment of the present invention includes a gating circuit, a demultiplexer, and an integrator. The gating circuit gates an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock. The demultiplexer demultiplexes the gated input sample to generate in-phase and quadrature samples. The integrator integrates the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively. Each of the in-phase and quadrature decimated samples having K bits.

Claims

1. An apparatus comprising:

a gating circuit to gate an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock, N being a positive integer;

a demultiplexer coupled to the gating circuit to demultiplex the gated input sample to generate in-phase and quadrature samples; and

an integrator coupled to the demultiplexer to integrate the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively, each of the in-phase and quadrature decimated samples having K bits, K being a positive integer.

2. The apparatus of claim 1 further comprising:

a mapper coupled to the integrator to map the in-phase and quadrature decimated samples into in-phase and quadrature demodulated samples, respectively, the in-phase and quadrature demodulated samples having L bits, L being less than K, L being a positive integer.

3. The apparatus of claim 2 wherein the gating circuit comprises:

a frequency divider to divide the sampling clock by N to generate the first clock; and

an exclusive OR gate coupled to the frequency divider to perform an exclusive OR operation on the input sample and the first clock, the exclusive ORed input sample and the first clock corresponding to the gated input sample.

4. The apparatus of claim 2 wherein the demultiplexer comprises:

a first synchronizer coupled to the gating circuit to synchronize the gated input sample with a second clock, the second clock being N/2 times faster than the first clock, the first synchronizer generating the in-phase sample; and

a second synchronizer coupled to the gating circuit to synchronize the gated input sample with a third clock, the third clock being complementary to the second clock, the second synchronizer generating the quadrature sample.

5. The apparatus of claim 4 wherein the integrator comprises:

a first counter coupled to the first synchronizer to count first logic levels in the in-phase sample in a first integration interval, the counted first logic levels corresponding to the in-phase decimated sample; and

a second counter coupled to the second synchronizer to count first logic levels in the quadrature sample in a second integration interval, the counted first logic levels corresponding to the in-phase decimated sample.

6. The apparatus of claim 5 wherein the first and second integration intervals are equal.

7. The apparatus of claim 6 wherein the first and second counters are clocked by one of the second and third clocks.

8. The apparatus of claim 5 wherein the mapper comprises:

a first combinational circuit coupled to the first counter to convert the K-bit in-phase decimated sample into the L-bit in-phase demodulated sample; and

a second combinational circuit coupled to the second counter to convert the K-bit quadrature decimated sample into the L-bit quadrature demodulated sample.

9. The apparatus of claim 8 wherein the input sample is one-bit.

10. The apparatus of claim 9 wherein K=3 and L=2.

11. A method comprising:

gating an input sample with a first clock, the input sample being clocked by a sampling clock N times faster than the first clock, N being a positive integer;

demultiplexing the gated input sample to generate in-phase and quadrature samples; and

integrating the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively, each of the in-phase and quadrature decimated samples having K bits, K bits being a positive integer.

12. The method of claim 11 further comprising:

mapping the in-phase and quadrature decimated samples into in-phase and quadrature demodulated samples, respectively, the in-phase and quadrature demodulated samples having L bits, L being less than K, L being a positive integer.

13. The method of claim 12 wherein gating the input sample comprises:

dividing the sampling clock by N to generate the first clock; and

performing an exclusive OR operation on the input sample and the first clock, the exclusive ORed input sample and the first clock corresponding to the gated input sample.

14. The method of claim 12 wherein demultiplexing the gated input sample comprises:

synchronizing the gated input sample with a second clock, the second clock being N/2 times faster than the first clock, the first synchronizer generating the in-phase sample; and

synchronizing the gated input sample with a third clock, the third clock being complementary to the second clock, the second synchronizer generating the quadrature sample.

15. The method of claim 14 wherein integrating the in-phase and quadrature samples comprises:

counting first logic levels in the in-phase sample in a first integration interval, the counted first logic levels corresponding to the in-phase decimated sample; and

counting first logic levels in the quadrature sample in a second integration interval, the counted first logic levels corresponding to the in-phase decimated sample.

16. The method of claim 15 wherein the first and second integration intervals are equal.

17. The method of claim 16 wherein the first and second counters are clocked by one of the second and third clocks.

18. The method of claim 15 wherein mapping comprises:

converting the K-bit in-phase decimated sample into the L-bit in-phase demodulated sample by a first combinational circuit; and

converting the K-bit quadrature decimated sample into the L-bit quadrature demodulated sample a second combinational circuit.

19. The method of claim 18 wherein the input sample is one-bit.

20. The method of claim 19 wherein K=3 and L=2.

21. A receiver comprising:

a radio frequency (RF) front end circuit to receive an RF signal from a global positioning system (GPS) satellite, the RF front end circuit sampling the RF signal at a sampling clock to provide an input sample; and

a demodulator coupled to the RF front end circuit to demodulate the received RF signal, the demodulator comprising;

a gating circuit to gate the input sample with a first clock, the sampling clock being N times faster than the first clock, N being a positive integer,

a demultiplexer coupled to the gating circuit to demultiplex the gated input sample to generate in-phase and quadrature samples; and

an integrator coupled to the demultiplexer to integrate the in-phase and quadrature samples to generate in-phase and quadrature decimated samples corresponding to the in-phase and quadrature samples, respectively, each of the in-phase and quadrature decimated samples having K bits, K being a positive integer.

22. The receiver of claim 21 wherein the demodulator further comprising:

a mapper coupled to the integrator to map the in-phase and quadrature decimated samples into in-phase and quadrature demodulated samples, respectively, the in-phase and quadrature demodulated samples having L bits, L being less than K, L being a positive integer.

23. The receiver of claim 22 wherein the gating circuit comprises:

a frequency divider to divide the sampling clock by N to generate the first clock; and

an exclusive OR gate coupled to the frequency divider to perform an exclusive OR operation on the input sample and the first clock, the exclusive ORed input sample and the first clock corresponding to the gated input sample.

24. The receiver of claim 22 wherein the demultiplexer comprises:

a first synchronizer coupled to the gating circuit to synchronize the gated input sample with a second clock, the second clock being N/2 times faster than the first clock, the first synchronizer generating the in-phase sample; and

a second synchronizer coupled to the gating circuit to synchronize the gated input sample with a third clock, the third clock being complementary to the second clock, the second synchronizer generating the quadrature sample.

25. The receiver of claim 24 wherein the integrator comprises:

a first counter coupled to the first synchronizer to count first logic levels in the in-phase sample in a first integration interval, the counted first logic levels corresponding to the in-phase decimated sample; and

a second counter coupled to the second synchronizer to count first logic levels in the quadrature sample in a second integration interval, the counted first logic levels corresponding to the in-phase decimated sample.

26. The receiver of claim 25 wherein the first and second integration intervals are equal.

27. The receiver of claim 26 wherein the first and second counters are clocked by one of the second and third clocks.

28. The receiver of claim 25 wherein the mapper comprises:

a first combinational circuit coupled to the first counter to convert the K-bit in-phase decimated sample into the L-bit in-phase demodulated sample; and

a second combinational circuit coupled to the second counter to convert the K-bit quadrature decimated sample into the L-bit quadrature demodulated sample.

29. The receiver of claim 28 wherein the input sample is one-bit.

30. The receiver of claim 29 wherein K=3 and L=2.