Apparatus and method for controlling a master/slave system via master device synchronization

• US 6,839,393 B1
• Filed: 07/14/1999
• Issued: 01/04/2005
• Est. Priority Date: 07/14/1999
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Sidiropoulos, Stefanos
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US09/353,547
• Time in Patent Office: 2,001 Days
• Field of Search: 375/371, 375/356, 375/358, 375/372, 327/141, 327/155, 327/158, 327/161, 327/162
• US Class Current: 375/371
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 13/4217 with synchronous protocol
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.

Claims

1. A method of operating a master/slave system, said method comprising the steps of:

identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner;

transferring data from said slave device to said master device in accordance with said master receive data phase value;

characterizing a master transmit data phase value to coordinate the transfer of data from said master device to said slave device; and

routing data from said master device to said slave device in accordance with said master transmit data phase value.

2. The method of claim 1 wherein said identifying step includes the steps of:

applying an alignment signal from said slave device to said master device; and

aligning a receive data clock signal with said alignment signal to obtain said master receive data phase value.

3. The method of claim 2 wherein said identifying step further includes the steps of:

applying a margin offset to said master receive data phase value; and

storing said master receive data phase value.

4. The method of claim 1 wherein said transferring step includes the steps of:

adjusting a system clock signal in accordance with said master receive data phase value to obtain a master receive data clock; and

receiving data at said master device in response to said master receive data clock.

5. The method of claim 1 wherein said characterizing step includes the steps of:

routing request bus data received at said slave device to said master device to form re-routed request bus data; and

aligning a receive data clock signal with said re-routed request bus data to obtain said master transmit data phase value.

6. The method of claim 5 wherein said characterizing step further includes the steps of:

applying a margin offset to said master transmit data phase value; and

storing said master transmit data phase value.

7. The method of claim 1 wherein said aligning step includes the steps of:

adjusting a system clock signal in accordance with said master transmit data phase value to obtain a master transmit data clock; and

transmitting data from said master device in response to said master transmit data clock.

8. A method of operating a master/slave system, said method comprising the steps of:

assessing a phase delay required for synchronized communication between a master device with a universal phase aligner and a slave device without phase alignment circuitry;

assigning, based upon said phase delay, a first data signal edge that said slave device does not process and a second data signal edge that said slave device does process; and

communicating data between said master device and said slave device in accordance with said phase delay.

9. The method of claim 8 wherein said assessing step includes the step of assessing a plurality of phase delays required for synchronized communication between said master device and a corresponding plurality of slave devices.

10. A method of operating a master/slave system, said method comprising the steps of:

assessing a plurality of phase delays for synchronized communication between a master device and a slave device, wherein each phase delay is associated with a different bus connecting the master device and the slave device;

identifying a phase delay from said plurality of phase delays for the slave device; and

communicating data between said master device and said slave device in accordance with said phase delay.

11. The method of claim 10 further comprising the step of designating the slave device for communication with said master device.

12. The method of claim 11 wherein said designating step includes the step of applying a control signal to a side band bus linking the master device and the slave device.

13. The method of claim 11 wherein said designating step includes the step of applying a control signal to a request bus linking the master device and the slave device.

14. A master/slave system, comprising:

a slave device; and

a master device coupled to the slave device and including an addressable phase value register bank adapted for storing a plurality of phase values for said slave device, said master device utilizing a selected phase value of said plurality of phase values to establish synchronous communication between said master device and the slave device.

15. The master/slave system of claim 14 wherein said master device utilizes a first selected phase value to establish a master receive data clock signal to receive data from the slave device.

16. The master/slave system of claim 15 wherein said master device utilizes a second selected phase value to establish a master transmit data clock signal to transmit data to the slave device.

17. The master/slave system of claim 14 wherein said master device performs a calibration operation in connection with to identify said plurality of phase values.

18. The master/slave system of claim 17 wherein said master device adds an offset value to each phase value of said plurality of phase values.

19. In a system comprising a master and at least one slave, the master and at least one slave coupled to a common bus, an auxiliary channel and a common clock, the method of phase aligning an internal clock in the master device and derived from the common clock to enable communication over the data bus with the at least one slave, the method comprising the steps of:

the master causing the at least one slave device to emit a periodic data signal on the data bus by sending a command to the at least one slave device on the auxiliary channel;

the master receiving and sampling the periodic data signal with the internal clock;

the master making a phase adjustment to the internal clock based on the sampled periodic signal to determine a phase boundary of the periodic data signal;

the master storing the value of the phase adjustment in a storage device of the master, and

the master adjusting the phase of the internal clock by the stored phase adjustment value plus an offset to receive data substantially without error from the at least one slave device.

20. A method for calibrating transmission of data from a master device to a slave device over multiple buses, comprising:

determining phase offset values corresponding to synchronous communication between the master device and the slave device over multiple buses;

storing the phase offset values in an addressable register bank in the master device to produce stored offset values; and

using the stored offset values in the synchronous communication between the master device and the slave device over at least one bus.

21. The method of claim 20, wherein using the stored offset value further comprises:

adjusting the phase of a clock signal based on at least one stored offset value to produce a phase adjusted clock signal; and

transmitting data over at least one bus based on the phase adjusted clock signal.

22. The method of claim 21, wherein transmitting data over at least one bus further comprises driving the data on the bus using an output buffer, wherein timing of the output buffer is controlled based on the phase adjusted clock signal.

23. The method of claim 20, wherein determining the phase offset value further comprises sending data to the slave device.

24. The method of claim 23, wherein the data is sent to the slave device over a request bus.

25. The method of claim 23, wherein determining the phase offset value further comprises receiving the data sent to the slave device, from the slave device.

26. The method of claim 25, wherein determining the phase offset value further comprises comparing the phase of the data received from the slave device with the phase of a clock signal.

27. The method of claim 26, wherein the data is sent to the slave device over a request bus, and wherein the data is received from the slave device over a data bus.

28. The method of claim 20, wherein the phase offset value is stored with a plurality of additional phase offset values in the master device.

29. The method of claim 20, wherein the phase offset value is adjusted by a margin offset.

34. The method of claim 20, wherein using the stored offset value further comprises using the stored offset value in the transmission of data over a plurality of data lines.

35. The method of claim 34, wherein using the stored offset value further comprises:

adjusting the phase of a clock signal based on the stored offset value to produce a phase adjusted clock signal; and

driving data on the plurality of data lines using a corresponding plurality of output buffers, wherein timing of each output buffer of the plurality of output buffers is controlled based on the stored offset value.

30. A method for calibrating transmission of data from a master device to a first slave device over a data line and a second slave device over a request line, comprising:

determining a phase offset value corresponding to data transmission from the master device to the first slave device over the data line and a control phase offset value corresponding to control information transmission from the master device to the second slave device over the request line;

storing the phase offset value and the control phase offset value in the master device to produce a stored offset value and a stored control offset value, respectively; and

using the stored offset value in the transmission of data from the master device to the first slave device over the data line and using the stored control offset value in the transmission of control information from the master device to the second slave device over the request line.

31. The method of claim 30, wherein using the stored control offset value further comprises:

adjusting the phase of a clock signal based on the stored control offset value to produce a phase adjusted clock signal; and

transmitting control information over the request line based on the phase adjusted clock signal.

32. The method of claim 31, wherein transmitting control information over the request line further comprises driving the control information on the request line using an output buffer, wherein the timing of the output buffer is controlled based on the phase adjusted clock signal.

33. The method of claim 30, wherein the control information includes a slave access request.

36. A method for calibrating transmission of information from a master device to a slave device, comprising:

determining a plurality of phase offset values for synchronizing communication between a master device and a slave device;

storing the phase offset values in an addressable phase value register bank;

retrieving a stored offset value from the addressable phase value register bank; and

using the stored offset value in the transmission of information from the master device to the slave device.

37. The method of claim 36, wherein using the stored offset value further comprises:

adjusting the phase of a clock signal based on the stored offset value to produce a phase adjusted clock signal; and

transmitting control information over a request line based on the phase adjusted clock signal.

38. The method of claim 37, wherein transmitting control information over the request line further comprises driving the control information on a data line using an output buffer, wherein timing of the output buffer is controlled based on the phase adjusted clock signal.

39. The method of claim 36, wherein determining the phase offset value further comprises sending data to the slave device.

40. The method of claim 39, wherein sending data to the slave device further comprises sending data to the slave device over a request line.

41. The method of claim 39, wherein determining the phase offset value further comprises receiving the data sent to the slave device, from the slave device.

42. The method of claim 41, wherein determining the phase offset value further comprises comparing phase of the data received from the slave device with phase of a clock signal.

43. The method of claim 42, wherein the data is sent to the slave device over a request line, and wherein the data is received from the slave device over a data line.

44. The method of claim 36, wherein the phase offset value is stored with a plurality of additional phase offset values in the master device.

45. The method of claim 36, wherein the phase offset value is adjusted by a margin offset.

46. The method of claim 36, wherein using the stored offset value further comprises using the stored offset value in the transmission of control information over a plurality of request lines.

47. The method of claim 46, wherein using the stored offset value further comprises:

adjusting the phase of a clock signal based on the stored offset value to produce a phase adjusted clock signal; and

driving control information on the plurality of request lines using a corresponding plurality of output buffers, wherein timing of each output buffer of the plurality of output buffers is controlled based on the stored offset value.

48. The method of claim 36, wherein the information transmitted to the slave device is a portion of an access request.

49. A master device operable to transmit data to a first slave device over a data line, the master device comprising:

a phase aligner operable to determine a phase offset value corresponding to data transmission from the master device to the first slave device over the data line, wherein the phase aligner includes an addressable phase value register bank operable to store the phase offset value as a stored offset; and

an output buffer operably coupled to the phase aligner, wherein the output buffer is operable to drive the data on the data line based on the stored offset in a first register of the addressable phase value register bank.

50. The master device of claim 49, wherein the phase aligner includes a phase rotator operable to receive a clock signal, wherein the phase rotator is operable to generate a phase adjusted clock signal from the clock signal based on the stored offset, wherein timing of the output buffer is controlled based on the phase adjusted clock signal.

51. The master device of claim 50, wherein the phase rotator includes a phase locked loop.

52. The master device of claim 50, wherein the phase rotator includes a delay locked loop.

53. The master device of claim 49, wherein the phase aligner periodically determines the phase offset value corresponding to data transmission and stores the periodically determined phase offset value in the first register.

54. The master device of claim 49, wherein the phase offset value is at least partially based on flight time of the data on the data line.

55. The master device of claim 49 further comprising a logic block operable to generate data that is sent to the first slave device in order to determine the phase offset value.

56. The master device of claim 49 further comprising receiving circuitry operable to receive data from the first slave device, wherein the data received from the first slave device is used by the phase aligner to determine the phase offset value.

57. The master device of claim 56, wherein the phase aligner is operable to compare the data received from the first slave device with a clock signal to determine the phase offset value.

58. The master device of claim 49 further comprising a plurality of output drivers coupled to the phase aligner, wherein each output driver of the plurality of output drivers drives data onto a corresponding data line based on the stored offset.

59. A master device operable to transmit data to a first slave device over a data line and control information to a second slave device over a request line, the master device comprising:

a phase aligner operable to determine a phase offset value corresponding to data transmission from the master device to the first slave device over the data line and a control phase offset value corresponding to control information transmission from the master device to the second slave device over the request line, wherein the phase aligner includes a first register operable to store the phase offset value as a stored offset and a second register operable to store the control phase offset value as a stored control phase offset;

a first output buffer operably coupled to the phase aligner, wherein the first output buffer is operable to drive the data on the data line based on the stored offset; and

a second output buffer operably coupled to the phase aligner, wherein the second output buffer is operable to drive the control information on the request line based on the stored control phase offset.

60. The master device of claim 59 further comprising a control output driver operably coupled to the phase aligner, wherein the control output driver is operable to drive control information on the request line based on the stored control offset.

61. The master device of claim 60, wherein the phase aligner includes a phase rotator operable to receive a clock signal, wherein the phase rotator is operable to generate a phase adjusted clock signal from the clock signal based on the control phase offset, wherein timing of the control output driver is controlled based on the phase adjusted clock signal.

62. The master device of claim 59 further comprising a plurality of control output drivers operably coupled to the phase aligner, wherein each control output driver of the plurality of control output drivers is operable to drive control information on a corresponding request line based on the stored control offset.

63. A master device operable to transmit control information to a first slave device over a request line, the master device comprising:

a phase aligner operable to determine a phase offset value corresponding to control information transmission from the master device to the first slave device over the request line, wherein the phase aligner includes an addressable phase value register bank operable to store the phase offset value as a stored offset; and

an output buffer operably coupled to the phase aligner, wherein the output buffer is operable to drive the control information on the request line based on the stored offset in a first register of the addressable phase value register bank.

64. The master device of claim 63, wherein the phase aligner includes a phase rotator operable to receive a clock signal, wherein the phase aligner is operable to generate a phase adjusted clock signal from the clock signal based on the stored offset, wherein timing of the output buffer is controlled based on the phase adjusted clock signal.

65. The master device of claim 64, wherein the phase rotator includes a phase locked loop.

66. The master device of claim 64, wherein the phase rotator includes a delay locked loop.

67. The master device of claim 63, wherein the phase aligner periodically determines the phase offset value corresponding to data transmission and stores the periodically determined phase offset value in the first register.

68. The master device of claim 63, wherein the phase offset value is at least partially based on flight time of the control information on the request line.

69. The master device of claim 63 further comprising a logic block operable to generate data that is sent to the first slave device in order to determine the phase offset value.

70. The master device of claim 63, further comprising receiving circuitry operable to receive data from the first slave device, wherein the data received from the first slave device is used by the phase aligner to determine the phase offset value.

71. The master device of claim 70, wherein the phase aligner is operable to compare the data received from the first slave device with a clock signal to determine the phase offset value.

72. The master device of claim 63 further comprising a plurality of output drivers coupled to the phase aligner, wherein each output driver of the plurality of output drivers outputs drives control information onto a corresponding request line based on the stored offset.

73. A method of operating a master/slave system, said method comprising the steps of:

assessing a plurality of phase delays required for synchronized communication between a master device and a plurality of slave devices over a shared communication channel, and storing corresponding information in a storage device;

identifying a selected phase delay from said plurality of phase delays for a selected slave device of said plurality of slave devices, and accessing the corresponding information from the storage device; and

communicating information over said shared communication channel between said master device and said selected slave device of said plurality of slave devices in accordance with said selected phase delay.

74. A master/slave system, comprising:

a plurality of slave devices, each slave device including a clock circuit without phase alignment circuitry; and

a master device with a universal phase alignment circuit including an addressable phase value register bank storing a plurality of phase values for said plurality of slave devices, said master device utilizing a selected phase value of said plurality of phase values to alter a system clock signal in accordance with said selected phase value so as to establish synchronous communication between said master device and a selected slave device of said plurality of slave devices over a shared communication channel coupling said master device to each of said plurality of slave devices.