Dynamically re-configurable CMOS imagers for an active vision system

• US 6,839,452 B1
• Filed: 11/22/2000
• Issued: 01/04/2005
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Guang, Pain, Bedabrata
• Primary Examiner(s): Johns, Andrew W.
• Assistant Examiner(s): NAKHJAVAN, SHERVIN K
• Application Number:
  US09/722,249
• Time in Patent Office: 1,504 Days
• Field of Search: 382/103, 348/169, 348/170, 348/171, 348/135, 348/137, 348/208.14
• US Class Current: 382/103
• CPC Class Codes: H03F 2200/375 Circuitry to compensate the offset being present in an amplifier
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence
• CPC Class Codes: H04N 25/443 by reading pixels from selected 2D regions of the array, e.g. for windowing or digital zooming
• CPC Class Codes: H04N 25/445 by skipping some contiguous pixels within the read portion of the array
• CPC Class Codes: H04N 25/46 by combining or binning pixels

Abstract

A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

Claims

1. A vision system, comprising:

a pixel array having an array of pixels, said array of pixels configured to receive light signals from an image having at least one tracking target;

at least one multi-resolution window operation circuit configured to process said image, each of said at least one multi-resolution window operation circuits arranged to process at least one tracking target within a particular respective one of a plurality of multi-resolution windows for an image frame, wherein a location of each multi-resolution window and its spatial resolution are programmable independently of the other multi-resolution windows; and

a pixel averaging circuit configured to sample and average pixels within said particular multi-resolution window.

2. The system of claim 1, further comprising:

a target detection circuit configured to receive and process said image such that said each of said at least one tracking target is assigned to said particular multi-resolution window.

3. The system of claim 1, wherein said multi-resolution window has a size between 1×

1 and 32×

32 pixels.

4. The system of claim 1, wherein said pixel averaging circuit includes a plurality of column-parallel capacitors.

5. The system of claim 1, further comprising:

at least one output analog signal chain, each of said at least one output analog signal chain configured to output signal from said particular multi-resolution window.

6. The system of claim 5, further comprising:

a plurality of latches, each latch configured to hold definition values of said particular multi-resolution window.

7. The system of claim 1, wherein each of said array pixels includes a poly-silicon gate biased in deep-depletion.

8. The system of claim 1, wherein said pixel averaging circuit includes a super-pixel configuration element that operates to sequentially average the pixels within a super-pixel, where said super-pixel is a group of pixels that is at least 2×

2 pixels in size.

9. The system of claim 1, further comprising:

row and column control circuits operating to appropriately arrange said light signal received by said pixel array.

10. A vision system, comprising:

a pixel array having an array of pixels, said array of pixels configured to receive light signals from an image having at least one tracking target;

at least one multi-resolution window operation circuit configured to process said image, each of said at least one multi-resolution window operation circuit arranged to process each of said at least one tracking target within a particular multi-resolution window; and

a pixel averaging circuit configured to sample and average pixels within said particular multi-resolution window,

wherein each of said at least one multi-resolution window operation circuit includes;

a super-pixel average address generation circuit configured to generate addresses of pixels within said super-pixel;

a mask generation circuit operating to provide a mask pattern for averaging pixels;

a switch network configured to input a super-pixel averaging address;

a super-pixel average address and row dump address generation block to provide average address and row dump address to said pixel averaging circuit; and

a capacitor bank control signal generation block configured to generate a control signal for said pixel averaging circuit.

11. The system of claim 10, wherein said switch network includes 32×

n switches, where n is a total number of columns.

12. The system of claim 11, wherein said switch network includes a diagonal control connection to ensure that averaging bit pattern is applied column-wise.

13. The system of claim 11, wherein said column control circuit further includes shift registers to shift and align each column of said pixel array to an actual starting address within said particular multi-resolution window.

14. A method for searching and tracking targets, comprising:

receiving light signals from an image having at least one tracking target;

detecting and separating said at least one tracking target into a respective one of a plurality of regions of interest for an image frame, wherein a location of each region of interest and its spatial resolution are programmable independently of the other regions of interest;

grouping each of said at least one region of interest into a plurality of blocks; and

first averaging pixels within each of said plurality of blocks.

15. The method of claim 14, where said first averaging includes sequentially averaging the pixels within a super-pixel, where said super-pixel is a group of pixels that is at least 2×

2 pixels in size.

16. The method of claim 14, wherein said first averaging is carried out in a passive capacitor array organized in column-parallel fashion.

17. The method of claim 14, wherein said first averaging includes block-averaging, said block-averaging including:

second averaging of a given row of pixel values;

storing an averaged value;

repeating said second averaging and storing for all rows, said repeating generating a plurality of row averages; and

computing an average of said plurality of row averages.

18. The method of claim 17, wherein said computing includes switching sample and hold capacitor in each column.