Computer architecture with caching of history counters for dynamic page placement

• US 6,839,739 B2
• Filed: 02/09/1999
• Issued: 01/04/2005
• Est. Priority Date: 02/09/1999
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Wilson, Kenneth Mark
• Primary Examiner(s): Barot, Bharat
• Assistant Examiner(s): Tran, Philip B.
• Application Number:
  US09/246,479
• Publication Number:
  US 20020049824A1
• Time in Patent Office: 2,156 Days
• Field of Search: 709/213, 709/214, 709/215, 711118-122, 711/100, 711/170, 711147-148
• US Class Current: 709/213
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/122 of the least frequently used [LFU] type, e.g. with individual count value
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.

Claims

1. A computer architecture comprising:

a local and a remote memory;

a remote processor operatively connected close to said remote memory and remote from said local memory to access said local and remote memories; and

local means operatively associated with and operatively connected close to said local memory, said local means operatively connected to and remote from said remote processor for counting the accesses of predetermined portions of said local memory only by said remote processor whereby only accesses by said remote processor are used to determine dynamic placement of said predetermined portions of local memory.

2. The computer architecture as claimed in claim 1 including:

a local processor operatively connected close to said local memory and remote from said remote memory to access said local and said remote memories; and

remote means operatively associated with and operatively connected to said remote memory, said remote means operatively connected to and remote from said local memory for counting only the accesses of predetermined portions of said remote memory by said local processor whereby only accesses by said local processor are used to determine dynamic placement of said predetermined portions of remote memory.

3. The computer architecture as claimed in claim 2 wherein:

said predetermined portions of said local and remote memories are pages of information; and

said local and remote caches of history counters provide access information for dynamic page placement of said pages of information.

4. The computer architecture as claimed in claim 3 including:

a system for replicating said pages of information in said local and remote memories under a first predetermined set of conditions and for migrating said pages of information between said local and remote memories under a second set of predetermined conditions.

5. The computer architecture as claimed in claim 1 wherein:

a local processor operatively connected close to said local memory and remote from said remote memory to access said local and said remote memories;

said local means contains a plurality of counters; and

said local means prevents counting of accesses by said local processor to portions of said predetermined portions of said local memory not represented by one of said plurality of counters contained therein.

6. The computer architecture as claimed in claim 1 wherein:

said local means is capable of containing a plurality of entries, each of said plurality of entries representative of a page in said memory.

7. The computer architecture as claimed in claim 1 wherein:

said local means is capable of containing a predetermined plurality of entries and a new entry in excess of said predetermined plurality of entries is capable of replacing one of said predetermined plurality of entries by a method selected from a group consisting of replacing an unused entry, replacing an entry having the lowest rate of accesses to memory, replacing an entry having the least recent use, and replacing a random entry.

8. The computer architecture as claimed in claim 1 wherein:

said local means is capable of containing a predetermined plurality of entries and an entry replaced by a new entry is stored in said local memory.

9. The computer architecture as claimed in claim 1 wherein:

said local means has a register therein only for remote accesses having fields consisting of a valid, address, counter, migration counter, write counter, page size, and a combination thereof.

10. The computer architecture as claimed in claim 1 wherein:

said local memory includes a memory controller operatively located therewith; and

said local means is operatively disposed in an element selected from a group consisting of said memory, said memory controller, said processor, said interconnect, and combinations thereof.

21. The computer architecture as claimed in claim 1 wherein:

said predetermined portions of said local memory have individual identifications; and

said local means contains individual entries for less than all of the individual identifications of said predetermined portions of local memory and only said individual entries of the most frequently accessed of said predetermined portions of local memory are maintained in said local means.

11. A computer architecture comprising:

a plurality of memories;

a plurality of processors operatively connected to access said plurality of memories;

each memory and processor of said plurality of processors and memories defining a plurality of uniform memory access cells;

said plurality of uniform memory access cells operatively connected to an interconnection network; and

a plurality of cache of history counters, each of said plurality of cache of history counters operatively associated with one of said plurality of uniform memory access cells and said interconnection network for tracking the accesses of predetermined portions of said plurality of memories only by said plurality of processors not in said uniform memory cell whereby only accesses from outside the uniform memory cell are used to determine dynamic placement of said predetermined portions of memory.

12. The computer architecture as claimed in claim 11 wherein:

each of said plurality of cache of history counters counts the memory accesses by each of said plurality of processors remote therefrom of predetermined portions of each of said plurality of memories local thereto.

13. The computer architecture as claimed in claim 12 wherein:

said predetermined portions of each of said plurality of memories are memory pages; and

said plurality of cache of history counters provide memory access information for dynamic page placement of said memory pages in said plurality of memories.

14. The computer architecture as claimed in claim 13 including:

an operating system using information from said local and remote cache of history counters for replicating said memory pages selected locations in said plurality of memories under a first predetermined set of conditions, modifying replicated memory pages under a second predetermined set of conditions, and for migrating said memory pages of information among said plurality of memories under a third set of predetermined conditions.

15. The computer architecture as claimed in claim 11 wherein:

one of said plurality of processors is a local processor operatively connected close to a local memory and remote from a remote memory to access said local and said remote memories;

one of said plurality of caches of history counters is a local cache of history counters containing a plurality of counters; and

said local cache of history counters prevents counting of accesses by said local processor to portions of said predetermined portions of said local memory.

16. The computer architecture as claimed in claim 11 wherein:

each of said plurality cache of history counters is capable of containing a plurality of entries, each of said plurality of entries representative of a memory page in said memory.

17. The computer architecture as claimed in claim 11 wherein:

each of said plurality cache of history counters is capable of containing a predetermined plurality of entries and a new entry in excess of said predetermined plurality of entries is capable of replacing one of said predetermined plurality of entries by a method selected from a group consisting of replacing an unused entry, replacing an entry having the lowest rate of accesses to memory, replacing an entry having the least recent use, and replacing a random entry.

18. The computer architecture as claimed in claim 11 wherein:

each of said plurality of cache of history counters is capable of containing a predetermined plurality of entries and an entry replaced by a new entry is stored in said memory local to said cache of history counters.

19. The computer architecture as claimed in claim 11 wherein:

each of said plurality of cache of history counters has a register therein having a field consisting of a valid bit, an address, a plurality of counters only for each of said plurality of processors remote therefrom accessing said each of said local memories, a migration counter, a write counter, a page size field, and a combination thereof.

20. The computer architecture as claimed in claim 11 wherein:

each of said plurality of memories includes a memory controller operatively located therewith; and

said plurality of cache of history counters operatively disposed in elements selected from a group consisting of said memory, said memory controller, said processor, said interconnect, and combinations thereof.

22. The computer architecture as claimed in claim 11 wherein:

said predetermined portions of said plurality of memories have individual identifications; and

each of said plurality of cache of history counters in each uniform memory access cell contains less than all of the individual identifications of said predetermined portions of memory in each uniform memory access cell and each of said plurality of cache memory counters contains individual entries for only said individual identifications of the most frequently accessed of said predetermined portions of memory from outside each uniform memory access cell for each of said plurality of cache of history counters.