Computer architecture with caching of history counters for dynamic page placement
First Claim
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1. A computer architecture comprising:
- a local and a remote memory;
a remote processor operatively connected close to said remote memory and remote from said local memory to access said local and remote memories; and
local means operatively associated with and operatively connected close to said local memory, said local means operatively connected to and remote from said remote processor for counting the accesses of predetermined portions of said local memory only by said remote processor whereby only accesses by said remote processor are used to determine dynamic placement of said predetermined portions of local memory.
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Abstract
A multi-processor system using distributed memory is provided with a cache of history counters located within each memory controller. Each entry of the cache of history counters represents one page in memory that has the potential to increase system performance by migrating or replicating to other memory locations. The cache of history counters permits creating histories of local memory accesses by remote processors for purposes of dynamic page placement.
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Citations
22 Claims
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1. A computer architecture comprising:
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a local and a remote memory;
a remote processor operatively connected close to said remote memory and remote from said local memory to access said local and remote memories; and
local means operatively associated with and operatively connected close to said local memory, said local means operatively connected to and remote from said remote processor for counting the accesses of predetermined portions of said local memory only by said remote processor whereby only accesses by said remote processor are used to determine dynamic placement of said predetermined portions of local memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 21)
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11. A computer architecture comprising:
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a plurality of memories;
a plurality of processors operatively connected to access said plurality of memories;
each memory and processor of said plurality of processors and memories defining a plurality of uniform memory access cells;
said plurality of uniform memory access cells operatively connected to an interconnection network; and
a plurality of cache of history counters, each of said plurality of cache of history counters operatively associated with one of said plurality of uniform memory access cells and said interconnection network for tracking the accesses of predetermined portions of said plurality of memories only by said plurality of processors not in said uniform memory cell whereby only accesses from outside the uniform memory cell are used to determine dynamic placement of said predetermined portions of memory. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 22)
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Specification