Single-chip data processing apparatus incorporating an electrically rewritable nonvolatile memory and method of operating the same

• US 6,839,774 B1
• Filed: 10/20/2000
• Issued: 01/04/2005
• Est. Priority Date: 10/21/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yu, Bum-Seok, Ra, Sang-Joo, Kim, Jong-In, Ahn, Jong-Keun
• Primary Examiner(s): Fleming, Fritz
• Assistant Examiner(s): SORRELL, ERON J
• Application Number:
  US09/693,773
• Time in Patent Office: 1,537 Days
• Field of Search: 710/8, 710/10, 710/5, 710/14, 710/22, 710/104, 713/1, 713/100, 713/320
• US Class Current: 710/14
• CPC Class Codes: G05B 19/0426 Programming the control sequence
• CPC Class Codes: G05B 2219/23308 Transfer program from ram to eprom, flash, card
• CPC Class Codes: G05B 2219/23345 Memory is eeprom
• CPC Class Codes: G05B 2219/25265 Flash memory
• CPC Class Codes: G05B 2219/25341 Single chip programmable controller
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller includes an electrically erasable and programmable nonvolatile memory and a memory controller for controlling the nonvolatile memory. Upon writing a control program for the microcontroller and data into the nonvolatile memory pursuant to an externally provided NVM command or an internally issued program command, a CPU of the microcontroller does not intervene in controlling the nonvolatile memory. Particularly, in a programming mode set by the external program command, CPU, buses, and communication interfaces of the microcontroller are deactivated. Further, the memory controller receives a NVM command, an address and data from outside of the microcontroller for controlling an operation of the nonvolatile memory based on the NVM command and the address without intervention of the CPU.

Claims

1. A microcontroller comprising:

a plurality of buses;

a central processing unit (CPU) connected to said plurality of buses;

a system clock input in signal communication with said CPU for receiving a system clock signal;

a mode controller in signal communication with said CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection command;

at least one bussed communication interface selectively connected to said plurality of buses;

an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program;

a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal; and

a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said at least one bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals.

2. The microcontroller of claim 1, wherein the NVM command indicates an internal operation of said NVM comprising a read operation, a write operation and an erase operation.

3. The microcontroller of claim 2, wherein said NVM controller receives an NVM command and address in either one of the read operation or the erase operation.

4. The microcontroller of claim 2, wherein said NVM controller receives a set of an NVM command, an address and data in the write operation.

5. The microcontroller of claim 1, wherein said CPU is halted and remains in an inactive state during a programming mode wherein said memory controller controls the internal operation of said NVM.

6. The microcontroller of claim 5, wherein said memory controller serially receives the NVM command and said at least one of an address and data from outside of said microcontroller via the serial interface.

7. The microcontroller of claim 5, wherein the received data is a control program set which includes a list of program instructions and program data for programming said microcontroller.

8. The microcontroller of claim 5, wherein said memory controller serially receives a control program set and data, and writes the control program set and data in parallel into said NVM.

9. The microcontroller of claim 1, wherein said CPU receives and decodes an NVM command of an internal operation from said at least one communication interface to write a plurality of control bits of said NVM controller in response to a decoded NVM command.

10. The microcontroller of claim 9, wherein said memory controller halts said CPU in response to the write command provided from said CPU while the update program is being written into said NVM.

11. The microcontroller of claim 9, wherein said serial interface included in said memory controller remains in an inactive state.

12. The microcontroller of claim 9, further comprising at least one of a register file included in said CPU and a data buffer included in said NVM for temporarily storing a control program set and data.

13. The microcontroller of claim 1, said memory controller further comprising a set of control register, address register and data register operatively connected to one of said buses or said serial interface.

14. The microcontroller of claim 13, wherein the control register, address register and data register are coupled to an address bus through an address decoder.

15. The microcontroller of claim 13, said memory controller further comprising a multiplexer for selectively outputting one of an address bus of said buses, and an output of the address register in response to an address selection signal from said control register.

16. The microcontroller of claim 13, said memory controller further comprising a sector protection flag register to prevent false writing into a write-inhibited cell sector.

17. The microcontroller of claim 1, wherein said program/erase timing controller includes a clock generator for generating a program/erase synchronous clock signal independent of a main clock applied to said microcontroller.

18. A microcontroller comprising:

a central processing unit (CPU) connected to a plurality of buses;

a system clock input in signal communication with said CPU for receiving a system clock signal;

a mode controller in signal communication with the CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection signal;

a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;

a memory device in signal communication with the CPU for storing data and control program, said memory device being the only memory in the microcontroller and consisting essentially of an electrically rewritable nonvolatile memory (NVM);

a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal; and

a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals.

19. The microcontroller of claim 18, wherein said memory controller further includes a serial interface for serially receiving command, data and address for reading from or writing to the memory device without intervention from the CPU.

20. The microcontroller of claim 18, wherein during one programming mode, the CPU moves addresses and data from the communication interface to the memory controller and the memory controller performs a read or write operation with the memory device without intervention from the CPU.

21. A microcontroller comprising:

a central processing unit (CPU) connected to a plurality of buses;

a system clock input in signal communication with said CPU for receiving a system clock signal;

a mode controller for generating mode control signals to set operation modes of said microcontroller in response to a mode selection signal;

a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;

an electrically rewritable nonvolatile memory (NVM) being the only memory in the microcontroller for storing data and control program;

a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal; and

a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively in response to the mode control signals wherein during one mode of operation, the memory controller directly reads from and writes to the NVM with said data and address without intervention from the CPU.

22. A microcontroller comprising:

a central processing unit (CPU) connected to a plurality of buses;

a system clock input in signal communication with said CPU for receiving a system clock signal;

a mode controller in signal communication with the CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection signal;

a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;

an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program;

a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal; and

a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals, wherein during one mode of operation, the memory controller halts the CPU and directly reads from and writes to the NVM with said data and address.

23. A microcontroller comprising:

a plurality of buses;

a central processing unit (CPU) connected to said plurality of buses;

a mode controller in signal communication with said CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection command;

at least one bussed communication interface selectively connected to said plurality of buses;

an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program; and

a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said at least one communication unbussed serial interface and in a first programming mode for receiving an NVM command and at least one of address and data through either one of said at least one bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals;

wherein said CPU is halted and remains in an inactive state during an update operation of said NVM, thereby reducing the power consumption of said CPU.