System and method for transferring data over a communication medium using data transfer links

• US 6,839,777 B1
• Filed: 09/11/2000
• Issued: 01/04/2005
• Est. Priority Date: 09/11/2000
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Vrancic, Aljosa, Madden, David W.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Chen, Alan S
• Application Number:
  US09/659,914
• Time in Patent Office: 1,576 Days
• Field of Search: 710/8, 710/10, 710/11, 710/14, 710/22, 710/52
• US Class Current: 710/52
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2213/0012 High speed serial bus, e.g. IEEE P1394

Abstract

A system and method for transferring data over a communications medium using data transfer links. A host computer may couple to a device through a serial bus. A buffer of contiguous virtual memory addresses may correspond to non-contiguous physical addresses, which may be stored in a linked list of transfer nodes, preserving the order of the original virtual buffer elements. Each transfer node specifies a data transfer between the host and device, and may be executed by the device DMA Controller. Each node may contain source and/or destination address information, size of the data to be transferred, and a link to the next node. The transfer nodes may be transferred to the device using a double-buffering scheme wherein the device executes the nodes from one half of the link buffer while the host computer transfers further nodes to be executed to the other half of the link buffer. The buffer halves may be switched back and forth between these two processes until all links are executed. To prevent overruns, safety and message links may be inserted into the transfer link list. The safety link may prevent the DMA channel from executing the next half of the link list until it has been updated by the host. The safety link may then be turned into a connection link. The host may update the used half of the link chain only after it receives a message initiated by the message link that the DMA Channel is done with its half of the linked list.

Claims

1. A method for transferring data in a system including a host computer system coupled through a communication medium to a data acquisition device, the method comprising:

configuring a data acquisition device for a data input/output (I/O) operation, wherein the data acquisition device comprises a link buffer;

the host computer system preparing a plurality of transfer links, wherein each of the plurality of transfer links specifies a transfer of data between the data acquisition device and the host computer system;

transferring a first portion of the plurality of transfer links from the host computer system to a first portion of the link buffer of the data acquisition device over the communication medium;

the data acquisition device initiating the data I/O operation;

the data acquisition device executing the first portion of the plurality of transfer links from the first portion of the link buffer to transfer data between a data buffer in the data acquisition device and host memory in the host computer system; and

transferring a second portion of the plurality of transfer links from the host computer system to a second portion of the link buffer of the data acquisition device over the communication medium, wherein at least a portion of said transferring the second portion of the plurality of transfer links and at least a portion of said executing the first portion of the plurality of transfer links are performed concurrently.

2. The method of claim 1, wherein said transferring the first portion of the plurality of transfer links to the first portion of the link buffer of the data acquisition device comprises the data acquisition device fetching the first portion of the plurality of transfer links to the first portion of the link buffer of the data acquisition device.

3. The method of claim 1,

wherein the data acquisition device initiating the data I/O operation comprises the host computer initiating a data acquisition process on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device executing the first portion of the plurality of transfer links from the first portion of the link buffer comprises;

the data acquisition device acquiring data and storing the data in the data buffer; and

the DMA Controller executing the first portion of the plurality of transfer links to transfer the data over the communication medium to the host memory in the host computer.

4. The method of claim 1,

wherein the data acquisition device initiating the data I/O operation comprises the host computer initiating a data acquisition process on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device executing the first portion of the plurality of transfer links from the first portion of the link buffer comprises;

the data acquisition device notifying the DMA Controller;

the data acquisition device requesting data from the DMA Controller; and

the DMA Controller executing the first portion of the plurality of transfer links to transfer the data from the host memory in the host computer system to the data buffer of the data acquisition device.

5. The method of claim 1, further comprising:

the data acquisition device executing the second portion of the plurality of transfer links from the second portion of the link buffer to transfer data between the data buffer in the data acquisition device and host memory in the host computer system; and

transferring a third portion of the plurality of transfer links from the host computer system to the first portion of the link buffer of the data acquisition device over the communication medium, wherein at least a portion of said transferring the third portion of the plurality of transfer links and at least a portion of said executing the second portion of the plurality of transfer links are performed concurrently.

6. The method of claim 5,

wherein the data acquisition device alternates between executing all transfer links from the first portion of the link buffer and all transfer links from the second portion of the link buffer, while the host computer system alternates between transferring transfer links from the host computer system to the second portion of the link buffer and transferring transfer links from the host computer system to the first portion of the link buffer, until there are no more transfer links to transfer from the host computer system.

7. The method of claim 6,

wherein each transfer link comprises at least one of a source address or a destination address, a count of a number of bytes in the transfer, and a pointer to a subsequent transfer link.

8. The method of claim 6,

wherein one or more of the plurality of transfer links comprises a self configuration link, wherein the self configuration link comprises one or more instructions to move data to, from, or between DMA Controller registers of a DMA Controller.

9. The method of claim 8,

wherein the self configuration link is inserted at the end of the first portion of the plurality of transfer links;

and

wherein the DMA Controller executes the first portion of the plurality of transfer links on a DMA channel;

the method further comprising;

if the DMA channel reaches the self configuration link before the host computer system has finished transferring the second portion of the plurality of transfer links to the second portion of the link buffer, the self configuration link stopping the DMA channel to prevent data overruns.

10. The method of claim 8,

wherein the self configuration link is inserted at the end of the second portion of the plurality of transfer links;

and

wherein the DMA Controller executes the second portion of the plurality of transfer links on a DMA channel;

the method further comprising;

if the DMA channel reaches the self configuration link before the host computer has finished transferring the third portion of the plurality of transfer links to the first portion of the link buffer, the self configuration link stopping the DMA channel to prevent data overruns.

11. The method of claim 8,

wherein the self configuration link is inserted in the first portion of the plurality of transfer links;

and

wherein the DMA Controller executes the first portion of the plurality of transfer links on a DMA channel;

the method further comprising;

when the DMA channel reaches the self configuration link, notifying the host computer system to begin transferring the second portion of the plurality of transfer links to the second portion of the link buffer.

12. The method of claim 8,

wherein the self configuration link is inserted in the second portion of the plurality of transfer links;

and

wherein the DMA Controller executes the second portion of the plurality of transfer links on a DMA channel;

the method further comprising;

when the DMA channel reaches the self configuration link, notifying the host computer system to begin transferring the third portion of the plurality of transfer links to the first portion of the link buffer.

13. The method of claim 1,

wherein the communication medium comprises an IEEE 1394 bus, which is compliant with an IEEE 1394 protocol specification.

14. The method of claim 13,

wherein the data acquisition device comprises a PCI device,

wherein the data acquisition device further comprises a PCI/394 translator;

the method further comprising the PCI/1394 translator translating messages between the IEEE 1394 protocol and PCI, thereby providing a mechanism for communication between the IEEE 1394 bus and the PCI device.

15. A system for transferring data over a communication medium, the system comprising:

a data acquisition device coupled to a first end of the communication medium, wherein the data acquisition device comprises a link buffer; and

a host computer system coupled to a second end of the communication medium, wherein the host computer system is operable to communicate through the communication medium to the data acquisition device;

wherein the host computer system is further operable to prepare a plurality of transfer links and transfer a first portion of the plurality of transfer links to a first portion of the link buffer of the data acquisition device, wherein each of the plurality of transfer links specifies a transfer of data between the data acquisition device and the host computer system;

wherein the data acquisition device is operable to execute the first portion of the transfer links;

wherein the host computer system is further operable to transfer a second portion of the plurality of transfer links to a second portion of the link buffer of the data acquisition device; and

wherein at least a portion of said executing the first portion of the transfer links and at least a portion of said transferring the second portion of the plurality of transfer links to the second portion of the link buffer of the data acquisition device are performed concurrently.

16. The method of claim 15, wherein said host computer system being operable to transfer the first portion of the plurality of transfer links to the first portion of link buffer of the data acquisition device comprises the data acquisition device being operable to fetch the first portion of the plurality of transfer links to the first portion of the link buffer of the data acquisition device.

17. The system of claim 15,

wherein the host computer system is further operable to:

configure the data acquisition device for data input/output; and

initiate a data I/O operation on the data acquisition device, after the host computer system transfers the first portion of the plurality of transfer links to the first portion of the link buffer of the data acquisition device.

18. The method of claim 17,

wherein the host computer system being operable to initiate the data I/O operation comprises the host computer system being operable to initiate a data acquisition process on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device being operable to execute the first portion of the plurality of transfer links from the first portion of the link buffer comprises;

the data acquisition device being operable to acquire data and store the data in a data buffer in the data acquisition device; and

the DMA Controller being operable to execute the first portion of the plurality of transfer links to transfer the data over the communication medium to the host a memory in the host computer system.

19. The system of claim 17,

wherein the host computer system being operable to initiate the I/O operation on the data acquisition device comprises the host computer system being operable to initiate a data generation operation on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device being operable to execute the first portion of the plurality of transfer links from the first portion of the link buffer comprises;

the data acquisition device being operable to notify the DMA Controller;

the data acquisition device being operable to request data from the DMA Controller; and

the DMA Controller being operable to execute the first portion of the plurality of transfer links to transfer the data from a memory of the host computer system to a data buffer of the data acquisition device.

20. The system of claim 15, wherein the data acquisition device is further operable to execute the second portion of the plurality of transfer links from the second portion of the link buffer;

wherein the host computer system is further operable to transfer a third portion of the plurality of transfer links to the first portion of the link buffer;

wherein the data acquisition device is further operable to execute the second portion of the plurality of transfer links from the second portion of the link buffer; and

wherein at least a portion of said executing the second portion of the plurality of transfer links from the second portion of the link buffer and at least a portion of said transferring the third portion of the plurality of transfer links to the first portion of the link buffer are performed concurrently.

21. The system of claim 20,

wherein the data acquisition device is further operable to alternate between executing all transfer links from the first portion of the link buffer and all transfer links from the second portion of the link buffer, while the host computer system is further operable to alternate between transferring transfer links from the host computer system to the second portion of the link buffer and from the host computer system to the first portion of the link buffer, until there are no more transfer links to transfer from the host computer system.

22. The system of claim 15,

wherein each transfer link comprises at least one of a source address or a destination address, a count of a number of bytes in the transfer, and a pointer to a subsequent transfer link.

23. The system of claim 15,

wherein one or more of the plurality of transfer links comprises a self configuration link, wherein the self configuration link comprises one or more instructions to move data to, from, or between DMA Channel registers of a DMA Controller.

24. The system of claim 23,

wherein the self configuration link is inserted at the end of the first portion of the plurality of transfer links;

wherein the DMA Controller executes the first portion of the plurality of transfer links on a DMA channel; and

wherein if the DMA channel reaches the self configuration link before the host computer system has finished transferring the second portion of the plurality of transfer links to the second portion of the link buffer, the self configuration link stops the DMA channel to prevent data overruns.

25. The system of claim 23,

wherein the host computer system is further operable to transfer a third portion of the plurality of transfer links to the first portion of the link buffer;

wherein the self configuration link is inserted at the end of the second portion of the plurality of transfer links;

wherein, the DMA Controller executes the second portion of the plurality of transfer links on a DMA channel; and

wherein if the DMA channel reaches the self configuration link before the host computer system has finished transferring the third portion of the plurality of transfer links to the first portion of the link buffer, the self configuration link stops the DMA channel to prevent data overruns.

26. The system of claim 23,

wherein the self configuration link is inserted in the first portion of the plurality of transfer links;

wherein the DMA Controller is operable to execute the first portion of the plurality of transfer links on a DMA channel; and

wherein the DMA channel is operable to notify the host computer system to begin transferring the second portion of the plurality of transfer links to the second portion of the link buffer when the DMA channel reaches the self configuration link.

27. The system of claim 23,

wherein the host computer system is further operable to transfer a third portion of the plurality of transfer links to the first portion of the link buffer;

wherein the self configuration link is inserted in the second portion of the plurality of transfer links;

wherein the DMA Controller is operable to execute the second portion of the plurality of transfer links on a DMA channel; and

wherein the DMA channel is operable to notify the host computer system to begin transferring the third portion of the plurality of transfer links to the first portion of the link buffer when the DMA channel reaches the self configuration transfer link.

28. The system of claim 15,

wherein the communication medium comprises an IEEE 1394 bus, which is compliant with an IEEE 1394 protocol specification.

29. The system of claim 15,

wherein the data acquisition device comprises a PCI device,

wherein the data acquisition device further comprises a PCI/1394 translator;

and

wherein the PCI/1394 translator is operable to translate messages between the IEEE 1394 protocol and PCI, thereby providing a mechanism for communication between the IEEE 1394 bus and the PCI device.

30. A method for transferring data in a system including a host computer system coupled through a communication medium to a data acquisition device, the method comprising:

configuring a data acquisition device for a data input/output (I/O) operation, wherein the data acquisition device comprises a link buffer;

the host computer system preparing a linked list of transfer nodes, wherein each of the linked list of transfer nodes includes a true address of physical memory of the host computer system;

the host computer system preparing a plurality of transfer links, wherein each of the plurality of transfer links specifies a transfer node and a transfer of data between the data acquisition device and the host computer system;

the host computer system transferring the plurality of transfer links to the link buffer of the data acquisition device over the communication medium;

the data acquisition device initiating the data I/O operation; and

the data acquisition device executing the plurality of transfer links from the link buffer to transfer data between a data buffer in the data acquisition device and the physical memory of the host computer system;

wherein, for each transfer node of the linked list of transfer nodes, the true address of the transfer node corresponds to a virtual address of a buffer, wherein the buffer spans contiguous virtual addresses mapping to the physical memory of the host computer system, wherein an Nth transfer node corresponds to an Nth virtual address of the buffer.

31. The method of claim 30, wherein said transferring the plurality of transfer links to the link buffer of the data acquisition device over the communication medium comprises the data acquisition device fetching the plurality of transfer links to the link buffer of the data acquisition.

32. The method of claim 30,

wherein the data acquisition device initiating the data I/O operation comprises the host computer system initiating a data acquisition process on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device executing the plurality of transfer links from the link buffer comprises;

the data acquisition device acquiring data and storing the data in the data buffer; and

the DMA Controller executing the plurality of transfer links to transfer the data over the communication medium to the physical memory of the host computer system.

33. The method of claim 30,

wherein the data acquisition device initiating the data I/O operation comprises the host computer system initiating a data acquisition process on the data acquisition device;

wherein the data acquisition device comprises a DMA Controller; and

wherein the data acquisition device executing the plurality of transfer links from the link buffer comprises;

the data acquisition device notifying the DMA Controller;

the data acquisition device requesting data from the DMA Controller, and

the DMA Controller executing the plurality of links to transfer the data from the physical memory of the host computer to the data buffer in the data acquisition device.

34. The method of claim 30, further comprising:

the host computer system preparing a second linked list of transfer nodes, wherein each of the second linked list of transfer nodes includes a true address of the physical memory of the host computer system;

the host computer system preparing a second plurality of transfer links, wherein each of the second plurality of transfer links specifies a transfer node of the second linked list and a transfer of data between the data acquisition device and the host computer system; and

the host computer system transferring the second plurality of transfer links to the link buffer of the data acquisition device over the communication medium.

35. The method of claim 34,

wherein at least a portion of said executing the plurality of transfer links from the link buffer to transfer data between the data buffer in the data acquisition device and the physical memory of the host computer system and at least a portion of said transferring the second plurality of transfer links to the link buffer of the data acquisition device over the communication medium are performed concurrently.

36. The method of claim 34,

wherein, for each transfer node of the second linked list of transfer nodes, the true address of the transfer node corresponds to a virtual address of a buffer, wherein the buffer spans contiguous virtual addresses mapping to the physical memory of the host computer system, wherein an Mth transfer node corresponds to an Mth virtual address of the buffer.

37. The method of claim 34,

wherein said transferring the plurality of transfer links to the link buffer of the data acquisition device over the communication medium comprises transferring the plurality of transfer links to a first portion of the link buffer of the data acquisition device;

and

wherein said transferring the second plurality of transfer links to the link buffer of the data acquisition device over the communication medium comprises transferring the second plurality of transfer links to a second portion of the link buffer of the data acquisition device;

the method further comprising;

the data acquisition device executing the second plurality of transfer links from the second portion of the link buffer to transfer data between the data buffer in the data acquisition device and the physical memory of the host computer system;

the host computer system preparing a third linked list of transfer nodes, wherein each of the third linked list of transfer nodes includes a true address of the physical memory of the host computer system;

the host computer system preparing a third plurality of transfer links, wherein each of the third plurality of transfer links specifies a transfer node of the third linked list and a transfer of data between the data acquisition device and the host computer system; and

the host computer system transferring the third plurality of transfer links to the first portion of the link buffer of the data acquisition device over the communication medium.

38. The method of claim 37,

wherein at least a portion of said executing the second plurality of transfer links from the second portion of the link buffer to transfer data between the data buffer in the data acquisition device and the physical memory of, the host computer system and at least a portion of said transferring the third plurality of transfer links to the first portion of the link buffer of the data acquisition device over the communication medium are performed concurrently.

39. The method of claim 37,

wherein, for each transfer node of the third linked list of transfer nodes, the true address of the transfer node corresponds to a virtual address of a buffer, wherein the buffer spans contiguous virtual addresses mapping to the physical memory of the host computer system, wherein a Pth transfer node corresponds to a Pth virtual address of the buffer.

40. The method of claim 37,

wherein the data acquisition device alternates between executing all transfer links from the first portion of the link buffer and all transfer links from the second portion of the link buffer, while the host computer system alternates between transferring transfer links from the host computer system to the second portion of the link buffer and transferring transfer links from the host computer system to the first portion of the link buffer, until there are no more transfer links to transfer from the host computer system.

41. The method of claim 40,

wherein each transfer link comprises at least one of a source address or a destination address, a count of a number of bytes in the transfer, and a pointer to a subsequent transfer link.

42. The method of claim 40,

wherein one or more of the of transfer links comprises a self configuration link, wherein the self configuration link comprises one or more instructions to move data to, from, or between DMA Controller registers of a DMA Controller.

43. The method of claim 42,

wherein the self configuration link is inserted at the end of the plurality of transfer links;

wherein the DMA Controller executes the plurality of transfer links on a DMA channel; and

wherein if the DMA channel reaches the self configuration link before the host computer system has finished transferring the second plurality of transfer links to the second portion of the link buffer, the self configuration link stopping the DMA channel to prevent data overruns.

44. The method of claim 42,

wherein the self configuration link is inserted at the end of the second plurality of transfer links;

wherein the DMA Controller executes the second plurality of transfer links on a DMA channel; and

wherein if the DMA channel reaches the self configuration link before the host computer system has finished transferring the third plurality of transfer links to the first portion of the link buffer, the self configuration link will stop the DMA channel to prevent data overruns.

45. The method of claim 43,

wherein the self configuration link is inserted in the plurality of transfer links;

and

wherein the DMA Controller executes the plurality of transfer links on a DMA channel;

when the DMA channel reaches the self configuration link, notifying the host computer system to begin transferring the second plurality of transfer links to the second portion of the link buffer.

46. The method of claim 42,

wherein the self configuration link is inserted in the second plurality of transfer links;

and

wherein the DMA Controller executes the second plurality of transfer links on a DMA channel;

the method further comprising;

when the DMA channel reaches the self configuration link, notifying the host computer system to begin transferring the third plurality of transfer links to the first portion of the link buffer.

47. The method of claim 30,

wherein the communication medium comprises an IEEE 1394 bus, which is compliant with an IEEE 1394 protocol specification.

48. The method of claim 47,

wherein the data acquisition device comprises a PCI device;

and

wherein the data acquisition device further comprises a PCI/1394 translator;

the method further comprising;

the PCI/1394 translator translating messages between the IEEE 1394 protocol and PCI, thereby providing a mechanism for communication between the IEEE 1394 bus and the PCI device.