Method and apparatus for accelerating detection of serial bus device speed signals
First Claim
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1. A method of administering a serial bus, the method comprising the acts of:
- providing a speed signal register;
detecting a first speed signal received by the speed signal register, the first speed signal indicating a first speed code;
detecting a second speed signal received by the speed signal register, the second speed signal indicating a second speed code, the second speed code being different from the first speed code; and
validating a speed mode based on the order in which the speed signals were received.
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Abstract
A method and apparatus for accelerating detection of speed code signals, and in particular S400 signals, for IEEE Standard 1394-1995 serial bus devices. The present invention validates S400 mode immediately after detecting an S400 speed signal, or immediately after detecting an S400 speed signal following a first to S200 speed signal. The invention further provides S200 and S100 mode validation according to current implementations. Additionally, the invention does not require RX_DATA_PREFIX as a pre-requisite for signal detection.
80 Citations
6 Claims
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1. A method of administering a serial bus, the method comprising the acts of:
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providing a speed signal register;
detecting a first speed signal received by the speed signal register, the first speed signal indicating a first speed code;
detecting a second speed signal received by the speed signal register, the second speed signal indicating a second speed code, the second speed code being different from the first speed code; and
validating a speed mode based on the order in which the speed signals were received. - View Dependent Claims (2, 3, 4, 5)
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6. A computer-readable medium containing instructions, which, when executed by a computer, administer a serial bus by:
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communicating with a speed signal register;
detecting a first speed signal received by the speed signal register, the first speed signal indicating a first speed code;
detecting a second speed signal received by the speed signal register, the second speed signal indicating a second speed code, the second speed code being different from the first speed code; and
validating a speed mode based on the order in which the speed signals were received.
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Specification
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Current AssigneeApple Inc.
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Original AssigneeApple Computer Incorporated (Apple Inc.)
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InventorsDuckwall, William S.
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Primary Examiner(s)Lefkowitz, Sumati
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Application NumberUS10/214,285Publication NumberTime in Patent Office883 DaysField of Search710 8- 19, 710/100, 710300-304, 710104-106, 710/305US Class Current710/305CPC Class CodesG06F 13/4295 using an embedded synchroni...
