Data modem

• US 6,839,792 B2
• Filed: 05/13/2002
• Issued: 01/04/2005
• Est. Priority Date: 12/15/2000
• Status: Expired due to Term

• Current Assignee: Elbit Systems of America LLC (Elbit Systems Limited)
• Original Assignee: Innovative Concepts, Inc. (Elbit Systems Limited)
• Inventors: Long, Shawn, Smith, Troy, Smith, Gregory N., Woodward, Robert A., Weinberger, Barry P., Wexler, Michael M., Feldstein, Andy A.
• Primary Examiner(s): THAI, XUAN MARIAN
• Application Number:
  US10/142,875
• Publication Number:
  US 20030225955A1
• Time in Patent Office: 967 Days
• Field of Search: 710/306, 375/219, 375/222, 375/303, 375/309, 375/323, 375/324, 375/334, 375/229, 375/230, 375/231
• US Class Current: 710/306
• CPC Class Codes: H04M 11/066 Telephone sets adapted for data transmision

Abstract

An improved data modem (IDM) and method includes a communication processor module, a mass storage module, a power converter module, and one or more DSP modules. The communication processor module utilizes commercial off-the-shelf components as well as programmable logic devices (EPLD), which are programmed to provide a watchdog timer, programmable interrupt controller, flash page addressing, ISA bus decoder and controller, and various circuits and logic.

Claims

1. A data modem having a Communication Processor Module (CPM), wherein the CPM comprising:

a host central processing unit;

a host bus connected to the host central processing unit;

a system controller bridge connected to the central processing unit via the host bus;

a memory bus connected to the controller bridge;

a system memory connected to the controller bridge through the memory bus;

a peripheral component interconnect (PCI) bus connected to the controller bridge;

a peripheral component interconnect bridge interfaced with the controller bridge via the peripheral component interconnect bus;

flash memory connected to the peripheral component interconnect ridge; and

a first Erasable Programmable Logic Device (EPLD) connected to the interconnect bridge and the flash memory, wherein the first EPLD provides electronic circuits for at least a system reset controller which controls hardware resets and software resets in the data modem.

2. The data modem as recited in claim 1, further comprising:

a serial communication controller connected to the peripheral component interconnect bus, wherein the communication controller controls synchronous and asynchronous communication ports; and

a second EPLD connected to the serial communication controller, wherein the second EPLD device provides a synchronous port fix so as to effect synchronous communication from the serial communication controller, and

wherein the first EPLD device further provides an Industry Standard Architecture (ISA) bus decoder and controller, flash page addressing register, a programmable interrupt controller, and a watchdog timer.

3. The data modem as recited in claim 2, wherein the flash page addressing register in the first EPLD is a writable flash page register utilized to manipulate the flash memory so as to access more than 128 Kbytes of flash memory.

4. The data modem as recited in claim 2, wherein the programmable interrupt controller comprises seven asynchronous interrupt inputs and one asynchronous interrupt output, a 7-bit write/read interrupt mask register, and a 7-bit write/read interrupt pending register.

5. The data modem as recited in claim 4, wherein the 7-bit interrupt mask register is I/O mapped and word-readable, and wherein the 7-bit interrupt pending register is I/O mapped and word-readable/writable.

6. The data modem as recited in claim 2, wherein the first EPLD further comprises an IDM status level input so as to identify the system into which the CPM is inserted, wherein the system is either the data modem or a Joint Combat Information Terminal (JCIT).

7. The data modem as recited in claim 6, wherein the first EPLD further comprises a Ready Discrete bit and a Fail bit for providing system status that are I/O mapped, word-readable/writable, and resides at a predetermined address.

8. The data modem as recited in claim 2, wherein the ISA bus decoder comprises interface and control logic for a flash page register, MIL-STD-1553B interface controller, the programmable interrupt controller, the watchdog timer, modem status, system status comprising a ready discrete and a fail status, IDE reset inverter, and a hardware version register.

9. The data modem as recited in claim 8, wherein the MIL-STD-1553B interface controller provides a glueless interface between an IS bus and a MIL-STD-1553B remote terminal.

10. The data modem as recited in claim 2, wherein watchdog timer comprises a reset status bit which indicates that a watchdog reset has occurred when the bit is set, and wherein the watchdog timer generates a board reset in the event the timer is not software-reset.

11. The data modem as recited in claim 2, wherein the first EPLD further comprises a word readable, I/O mapped version register residing at a predetermined address and containing a version number of the EPLD.

12. The data modem as recited in claim 2, wherein the first EPLD further comprises an Integrated Drive Electronics (IDE) reset inverter, wherein the reset inverter generates an additional reset signal for an external MSM IDE drive.

13. The data modem as recited in claim 2, wherein the communication processor further comprises a Push-to-Talk control having at least four programmable inverters for controlling Ground SIP PTT lines.

14. The data modem as recited in claim 2, wherein the second EPLD further comprises four general-purpose inverters for asserting additional PTT lines.

15. The data modem as recited in claim 2, wherein the EPLD further comprises IEEE-1394 buffer control for use to control buffers us for IEEE-1394 interface.

16. The data modem as recited in claim 2, wherein the programmable interrupt controller comprises eight asynchronous interrupt inputs and one asynchronous interrupt output, a 16-bit write/read interrupt mask register, and a 16-bit write/read interrupt pending register.

17. The data modem as recited in claim 16, wherein the 16-bit interrupt mask register is I/O mapped and word-readable/writeable, and the 16-bit interrupt pending register is I/O mapped and word-readable/writable.

18. The data modem as recited in claim 16, wherein

the 16-bit interrupt pending register is positive and negative edge detectable and I/O mapped and word-readable/writable.

19. The data modem as recited in claim 16, wherein the 16-bit interrupt pending register comprises upper eight bits that are positive edge triggered and lower eight bits that are negative edge triggered, and wherein the interrupt pending register is I/O mapped and word-readable/writable.

20. The data modem of claim 1, wherein the host central processing unit is a Pentium-compatible microprocessor operable in real mode or protected mode.

21. The data modem as recited in claim 1, further comprising:

a second EPLD connected to the peripheral component interconnect bus;

at least one serial communications controller connected to the peripheral component interconnect bus;

a local area network controller connected to the peripheral component interconnect bus; and

an IEEE-1394 backplane interface connected to the peripheral component interconnect bus,

wherein the flash memory is programmable with a BIOS and a boot kernel.

22. The data modem as recited in claim 21, wherein the at least one serial communication controller is a 4-channel communications controller.

23. The data modem as recited in claim 22, wherein the second EPLD further comprises a synchronous port fix so as to allow the configuration of the at least one serial communication controller to initiate communication with an external radio source.

24. The data modem as recited in claim 23, wherein the synchronous port fix comprises:

a clock multiplexer having at least two inputs, an output and a selection signal input;

an internal clock source providing a clock signal to a first input of the multiplexer, and

a receive data delay connected to the output of the multiplexer wherein the clock multiplexer provides a selectability between an external radio clock, which provides a clock signal to a second input of the multiplexer, and the internal clock source, wherein the receive data delay is used for realigning the phase of multiplexed external radio clock with received data from an external radio source, and wherein the selection signal input is controlled by general purpose bits on the serial communication controller.

25. The CPM of claim 21, further comprising:

a Serial EEPROM interfaced with the local area network controller, wherein the local area network controller is in compliance with Ethernet protocol.

26. The CPM of claim 25, further comprising:

a Joint Test Action Group interface for in-circuit-emulation.

27. The data modem as recited in claim 1, further comprising:

a controller peripheral connected to the peripheral component interconnect bus providing a plurality of signals for the local bus.

28. The data modem as recited in claim 1, further comprising:

a serial communication controller connected to the PCI bus, wherein the communication controller controls synchronous and asynchronous communication ports; and

,

a digitally controlled switch providing a synchronous operational mode fix so as to effect synchronous communication between the serial communication controller and one or more synchronous devices.

29. The data modem as recited in claim 1, wherein the first EPLD further comprises a programmable interrupt controller, a local bus reset controller, and a regulator fault latch controller controlled by the system reset controller.

30. The data modem as recited in claim 29, wherein the local bus reset controller in the first EPLD is a programmable reset controller providing at least four independent reset outputs, wherein the local bus reset controller effects the resetting of one or more module.

31. The data modem as recited in claim 30, further comprises a the local bus reset control register that is I/O mapped and word-writeable.

32. The data modem as recited in claim 31, wherein the local bus reset control register generates a pulse from a single I/O mapped word write.

33. The data modem as recited in claim 32, wherein the local bus reset pulse is bypassed by the reset signal of the controller peripheral connected to the PCI bus used to provide a plurality of signals for the local bus.

34. The data modem as recited in claim 30, wherein, upon receiving a reset or interrupt signal from a module, at least the interrupting module is reset and a PCI re-enumeration is performed without resetting other modules or the entire data modem.

35. The data modem as recited in claim 29, wherein the regulator fault latch controller in the first EPLD is a hardware state-machine comprising of at least one input and one output used to reset a regulator, wherein the regulator is Low Dropout Regulator (LDO) for regulating Gunning Transistor Logic voltage of the CPM.

36. The data modem of claim 1, further comprising:

embedded auxiliary power source for maintaining an uninterruptible operation of the modem in case of a primary power fault.

37. The data modem of claim 36, wherein the auxiliary power comprises a hold-up capacitor, fuel cell, or a battery power cell.

38. A improved data modem, comprising:

a ruggedized housing comprising;

a backplane;

at least one communication processor module;

a mass storage module; and

a power converter module,

wherein the communication processor module comprises at least one EPLD providing a plurality of electronic circuits, and a Pentium-compatible micro processor;

wherein the mass storage module comprises at least one solid-state drive; and

wherein each of the modules is compliant with Standard Electronic Module Form Factor E and are interfaced with one another via the backplane,

wherein the communication processor module is hardware compatible with Joint Combat Information Terminal (JCIT), the hardware compatibility comprises electrical interfaces and flow control compatibility to allow the communication processor module to be functional when inserted in JCIT.

39. The improved data modem of claim 38, wherein the hardware compatibility further comprises keying compatibility and automatic detection means for effecting the detection of the communication processor module when inserted in JCIT.

40. The improved data modem of claim 38, wherein the mass storage module further comprises a 10/100 base-T Ethernet-compliant hub.

41. The improved data modem of claim 38, further comprising an Input/Output Module (IOM).

42. The improved data modem as recited in claim 38, wherein the backplane is a passive backplane providing an interconnection for plurality of modules using a local bus architecture.