Multi-bank scheduling to improve performance on tree accesses in a DRAM based random access memory subsystem

• US 6,839,797 B2
• Filed: 12/21/2001
• Issued: 01/04/2005
• Est. Priority Date: 12/21/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Calle, Mauricio, Ramaswami, Ravi
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): SONG, HUA JASMINE
• Application Number:
  US10/026,352
• Publication Number:
  US 20030120861A1
• Time in Patent Office: 1,110 Days
• Field of Search: 711/5, 711/105, 711/106, 711/151, 711/158, 711/168, 710/17, 710/28, 710/20, 710/21, 710 35- 36, 710 39- 40, 710/52
• US Class Current: 711/5
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system of memory management incorporates multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data. A tree memory controller controls data read and write accesses to each of the banks in each of the channels. A bank queue for each bank in each channel keeps track of bank availability. When read or write requests are received at the tree memory controller, the controller checks the availability of each bank in a channel, identifies a first available bank, and executes the read request from the first available bank. In response to a write request, the controller blocks all read requests once it has confirmed that data to be written is complete for the selected memory word length. As soon as each bank queue for read requests is empty, the controller initiates burst mode transfer of the completed data word to all banks concurrently.

Claims

1. A method of memory management, comprising:

providing multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data;

providing a tree memory controller for controlling data read and write accesses to each of the banks in each of the channels;

establishing a bank queue for each bank in each channel for designating bank availability;

sending read or write requests to the tree memory controller;

checking, at the tree memory controller, the availability of each bank in a channel;

identifying a first available bank; and

executing the read request from the first available bank;

wherein controlling a write access includes blocking all read requests;

confirming that data to be written is complete for the selected memory word length;

waiting for each bank queue to indicate bank availability for all banks;

initiating burst mode transfer of the completed data word to all banks concurrently.

2. The method of claim 1 wherein the memory devices comprise dynamic random access memory (DRAM) devices.

3. The method of claim 1 wherein the memory devices comprise fast cycle random access memory (FCRAM) devices.

4. The method of claim 1 wherein the banks of memory devices are organized into two independent channels.

5. A system, comprising:

multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data;

a tree memory controller for controlling data read and write accesses to each of the banks in each of the channels;

a bank queue for each bank in each channel for designating bank availability; and

means for sending read or write requests to the tree memory controller, said controller determining availability of a bank for reading data and executing the read request from a first available bank;

wherein the controller controls a write access by blocking all read requests, confirming that data to be written is complete for the selected memory word length, waiting for each bank queue to indicate bank availability for all banks, and initiating burst mode transfer of the completed data word to all banks concurrently.

6. The system of claim 5 wherein the controller suspends all read requests during processing of a write request.

7. The system of claim 6 wherein the controller writes to all memory banks concurrently.

8. The system of claim 7 wherein all memory banks contain identical data.

9. The system of claim 5 wherein the memory banks comprise dynamic random access memory devices.

10. The system of claim 5 wherein the memory banks comprise fast cycle random access memory devices.

11. The system of claim 5 wherein the banks of memory devices are arranged in two independent channels.

12. The system of claim 5 wherein the minimum number of memory banks is determined by the ratio of the random cycle time to the random bank access delay.

13. A method of memory management, comprising:

providing multiple banks of memory devices organized into independent channels wherein each bank of memory devices contains duplicate data;

providing a tree memory controller for controlling data read and write accesses to each of the banks in each of the channels;

establishing a read bank queue and a write bank queue for each bank in each channel for designating bank availability;

sending read or write requests to the tree memory controller;

checking, at the tree memory controller, the availability of each bank in a channel;

identifying a first available bank; and

executing the read request from the first available bank;

wherein controlling a write access includes blocking all read requests;

confirming that data to be written is complete for the selected memory word length;

waiting for each bank queue to indicate bank availability for all banks;

initiating burst mode transfer of the completed data word to all banks concurrently.