Mixed hardware/software architecture and method for processing xDSL communications

• US 6,839,889 B2
• Filed: 03/01/2001
• Issued: 01/04/2005
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Liu, Ming-Kang
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/797,793
• Publication Number:
  US 20010047465A1
• Time in Patent Office: 1,405 Days
• Field of Search: 716/7, 716/16, 716/18, 703/14, 703/17, 709/104, 709/105, 709/106, 710/6, 710/10, 710/14, 710/18, 712/3, 712/13, 712/201
• US Class Current: 716/105
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 12/2856 Access arrangements, e.g. Internet access asynchronous transfer mode networks H04L12/5601; broadband local area networks H04L12/2801; optical access or distribution networks H04Q11/0067; access to open networks H04L12/5691; digital subscriber line end-user equipment and bit-level processing of data on a PSTN-based network H04M11/00; home network gateways H04L12/2834; wireless access networks H04W
• CPC Class Codes: H04L 12/289 Single service
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 2012/6478 Digital subscriber line, e.g. DSL, ADSL, HDSL, XDSL, VDSL
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01
• CPC Class Codes: H04M 11/062 using different frequency bands for speech and other data
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.

Claims

1. A method of implementing a scaleable architecture for a communications system based on minimizing a total gate count for the communications system, the method comprising the steps of:

(a) dividing a communications transmission process into a set of N individual transmission tasks (T1, T2, . . . TN);

(b) determining a computational complexity (M1, M2, . . . MN) for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks;

(c) determining a number of gates and/or transistors required to implement each of said N individual transmission tasks using a hardware based computing circuit; and

(d) determining a number of gates and/or transistors required to implement each of said N individual transmission tasks using a software based computing circuit;

(e) determining a first effective number of MIPs per gate and/or transistor achievable with said hardware based computing circuit when performing each of said N individual transmission tasks;

(f) determining a second effective number of MIPs per gate and/or transistor achievable with said software based computing circuit;

(g) allocating X individual transmission tasks to said software based computing circuit, where 1>

=X>

N, so that said X individual transmission tasks are performed in software; and

(h) allocating all remaining N-X individual transmission tasks to said hardware based computing circuit so that said N-X individual transmission tasks are performed using dedicated hardware logic;

wherein steps (g) and (h) are performed by comparing said first effective number of MIPs with said second effective number of MIPs.

2. The method of claim 1 wherein steps (g) and (h) are used to develop an architecture for a logical processing pipeline.

3. The method of claim 1 wherein steps (g) and (h) are used for configuring a data transmission in the communications system.

4. The method of claim 1 wherein steps (g) and (h) are used for configuring an arrangement of software and dedicated hardware logic to be used as shared resources for a multi-port communications system in a form of a logical hybrid processing pipeline.

5. The method of claim 1 wherein steps (g) and (h) are used for configuring an arrangement of software and dedicated hardware logic to be used as shared resources for both a transmission process and a receive process.

6. The method of claim 1 wherein during steps (e) and (f) said first effective number of MIPs are each scaled by a time factor corresponding to a number of times said hardware based computing circuit is used during a transmission period.

7. A method of determining a scaleable architecture for a communications system based on minimizing a total gate count for the communications system, the method comprising the steps of:

(a) dividing a communications transmission process into a set of N individual transmission tasks (T1, T2, . . . TN), each of said N individual transmission tasks having an associated computational complexity (Ml, M2, . . . MN), said associated computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks;

(b) performing an evaluation of a set of P computational circuits (C1, C2 . . . CP) for processing said set of N individual transmission tasks, said set of P computational circuits P having an associated gate or transistor count (G1, G2 . . . GP) required for processing each of said set of N individual transmission tasks;

wherein said evaluation includes considering a set of P computational circuits that includes a combination of hardware based computing resources and software based computing resources to be interconnected in a logical hybrid pipeline that is shared by both a transmission process and a receive process;

(c) determining an effective number of instructions per second (MIPs) obtainable by each of said set of P computational circuits when performing at least one of said transmission tasks; and

(d) allocating said N individual transmission tasks to an optimal subset of one or more of said set of P computational circuits (C1, C2 . . . CP) based on a consideration of reducing a total gate or transistor count used for performing said communications transmission process, and such that at least one hardware based computing resource and at least one software based resource are selected from said set of P computational circuits.

8. The method of claim 7 wherein said optimal subset of one or more of said set of P computational circuits is determined for a system that includes a plurality of communications ports that share said optimal subset for performing a transmission process and a receive process.

9. The method of claim 8, wherein said optimal subset is implemented such that a total gate or transistor count is less than approximately 1 million per port.

10. The method of claim 9 further including a step of implementing the scaleable architecture in a system-on-a-chip (SOC) integrated circuit.

11. The method of claim 7 wherein said hardware based computing resources include individual ASIC task blocks connected through a local bus, and said software based computing resources include one or more general purpose processors connected through a separate bus, such that said N individual transmission tasks are processed in a logical hybrid pipeline with operations for a port being interleaved in time between said individual ASIC blocks and said one or more general purpose processors.

12. The method of claim 7 wherein during step (c), said effective number of MIPs are each scaled by a time factor corresponding to a number of times said hardware based computing resource is used during a transmission period.

13. A method of operating a multi-port communications system comprising the steps of:

(a) dividing a communications transmission process for each port in the multi-port communication system into a set of N individual transmission tasks;

(b) allocating each of said N individual transmission tasks for execution by a dedicated application specific integrated circuit (ASIC) or digital signal processor (DSP) based on a gate and/or transistor count required to implement each of said N individual transmission tasks using said ASIC or DSP respectively, and based on a total number of instructions per second (MIPs) achievable by said ASIC and DSP; and

(c) performing said N individual transmission tasks using a logical hybrid pipeline comprised of least both said ASIC and said DSP;

wherein a combination of hardwired logic stages and software based stages are used to effectuate said communications transmission process by interleaving and overlapping execution of said N individual tasks between said hardwired logic stages and software based stages.

14. The method of claim 13 wherein said N individual transmission tasks include signal processing operations for both a physical medium dependent layer and a transport convergence layer.

15. The method of claim 13, wherein a set of ASICs is used to perform a subset of said N individual transmission tasks, wherein subset is based on said set of ASICs having an effective number of MIPs per gate exceeding said DSP.

16. The method of claim 15 wherein during step (c), said effective number of MIPs are each scaled by a time factor corresponding to a number of times said hardwired logic stages are used during a transmission period.

17. A method of operating a communications system comprising the steps of:

(a) dividing a communications transmission process into N separate transmission tasks;

(b) performing a first set of tasks taken from said N separate transmission tasks using a application specific integrated circuit (ASIC) consisting of dedicated hardware logic; and

(c) performing a second set of tasks taken from said N separate transmission tasks using a digital signal processor (DSP) executing a series of digital signal processing instructions associated with said DSP;

wherein said first set of tasks performed by using said ASIC include those where said ASIC has a first task performance rating measured in effective MIPs per gate or transistor exceeding a second task performance rating achievable by said DSP for each task in said first set of tasks.

18. The method of claim 17 wherein a task performance rating of said ASIC is further based on a time sharing factor that specifies a number of times said ASIC is useable during a single transmission period.

19. The method of claim 18 wherein said time sharing factor is based on a number of independent ports that use said ASIC during a single transmission period.

20. The method of claim 18 wherein said time sharing factor is based on a number of distinct operations that said ASIC performs during a single transmission period.

21. A method of controlling a communications system having a plurality of communication ports comprising the steps of:

(a) dividing a communications process for a first communication port of said plurality of communication ports into N separate tasks;

(b) performing a first set of tasks taken from said N separate tasks for said first communication port using an application specific integrated circuit (ASIC) consisting of dedicated hardware logic; and

(c) perfoming a second set of tasks taken from said N separate tasks for said first communication port using a digital signal processor (DSP) executing a series of digital signal processing instructions associated with said DSP;

wherein in a first mode both of said ASIC and DSP are used to perform said N separate tasks for said first communication port, and in a second mode only said DSP is used to perform said N separate tasks, said first and second modes being selectable based on utilization of available processing resources in the communications system by communication ports other than the first communication port.

22. The method of claim 21 wherein during said second mode, power savings are achieved by shutting off power selectively to said ASIC.

23. The method of claim 21 wherein said first communications port requires a first number of MIPs to complete a first receive process for the first communication port, and requires a second number of MIPs to complete a first transmit process for the first communication port, and said DSP is adapted with sufficient processing power to handle both said first receive process and said first transmit process for said first communications port.

24. The method of claim 21 wherein said DSP is adapted with sufficient processing power to handle a second number of receive processes and a second number of transmit processes for a second number of communications ports, said second number of communication ports being based on a total number of MIPs achievable by said DSP.

25. A method of implementing a communications system having a plurality of communication ports comprising the steps of:

(a) dividing a communications process for a first communication port of said plurality of communication ports into N separate tasks; and

(b) performing a first set of tasks taken from said N separate tasks for said first communication port using an application specific integrated circuit (ASIC) consisting of dedicated hardware logic; and

(c) performing a second set of tasks taken from said N separate tasks for said first communication port using a digital signal processor (DSP) executing a series of digital signal processing instructions associated with said DSP;

wherein said ASIC and said DSP use a total number of gates and/or transistors that are less than that which would be required by one or more DSPs to perform said first set and second set of tasks.

26. The method of claim 25, wherein said total number of gates and/or transistors is less than 1 million per each communication port used in the communications system.

27. The method of claim 25, wherein said ASIC and DSP are both located in a single system-on-a-chip (SOC) integrated circuit.

28. A communications system having a plurality of communication ports comprising:

a plurality of communications ports using a communications process divided into N separate tasks;

an application specific integrated circuit (ASIC) consisting of dedicated hardware logic for performing a first set of tasks taken from said N separate tasks; and

a digital signal processor (DSP) executing a series of digital signal processing instructions associated with said DSP for performing a second set of tasks taken from said N separate tasks;

wherein said ASIC and said DSP use a total number of gates and/or transistors that are less than that which would be required by one or more DSPs alone to perform said first set and second set of tasks.

29. The system of claim 28, wherein said total number of gates and/or transistors is less than 1 million per each communication port used in the communications system.

30. The system of claim 28, wherein said ASIC and DSP are both located in a single system-on-a-chip (SOC) integrated circuit.

31. The system of claim 28, further including a common memory used by said ASIC and said DSP, said common memory being used by a host computing system using the communications system.

32. A scaleable architecture for a communications system, the scaleable architecture having a minimized total gate count and said architecture comprising:

a plurality of communications ports, each communication port handling a communications process by dividing said communications process into a set of N individual transmission tasks (T1, T2 . . . TN);

wherein each of said N individual transmission tasks has an associated computational complexity (M1, M2, . . . MN), said associated computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; and

a set of P computational circuits (C1, C2 . . . CP) for processing said set of N individual transmission tasks, each computational circuit having an associated gate or transistor count (G1, G2 . . . GP) required for processing a communications task from said set of N individual transmission tasks, and an associated effective number of number of instructions per second (MIPs) when performing said communications task;

wherein said set of P computational circuits includes a combination of hardware based computing resources and software based computing resources to be interconnected in a logical hybrid pipeline that is shared by both a transmission process and a receive process, with operations for each port being interleaved between said hardware based computing resources and software based computing resources;

further wherein said N individual transmission tasks are allocated for processing based on a comparison of said associated effective number of MIPs achievable by said hardware based computing resources and said software based computing resources.

33. The system of claim 32 wherein said hardware based computing resources include one or more interconnected ASICs having a shared local bus, and said software based computing resources include one or more general purpose processors.

34. The system of claim 32 wherein a total number of gates and/or transistors is less than 1 million per each communication port used in the communications system.

35. The system of claim 33, wherein said one or more interconnected ASICs and said one or more general purpose processors are both located in a single system-on-a-chip (SOC) integrated circuit.

36. The system of claim 32, wherein said hardware based computing resources include one or more ASICs that are used by more than one port during a single processing period for said communications process.

37. The system of claim 32, wherein said hardware based computing resources include one or more ASICs that perform both a transmission process and a receive process within a single processing period for said communications process.

38. A communications system having a plurality of communication ports, each communication port processing a data transmission by dividing said processing into a set of N separate tasks, the system comprising:

an application specific integrated circuit (ASIC) consisting of dedicated hardware logic for performing a first set of tasks taken from said N separate tasks for a first communication port; and

a digital signal processor (DSP) executing a series of digital signal processing instructions associated with said DSP for performing a second set of tasks taken from said N separate tasks for said first communication port;

wherein said ASIC and DSP are interconnected in a logical hybrid pipeline of common computing resources such that they perform processing for more than one of the plurality of communications ports, and such that said ASIC and DSP alternate executing one of said set of N separate tasks for each port;

wherein in a first mode, both said ASIC and DSP are used to perform said N separate tasks for said first communication port, and in a second mode only said DSP is used to perform said N separate tasks, said first and second modes being selectable based on utilization of available processing resources in the communications system by communication ports other than the first communication port.

39. The system of claim 38 wherein during said second mode, power savings are achieved by shutting off power selectively to said ASIC and/or reducing a clock rate used by said logical pipeline.

40. The system of claim 38 wherein said first communication port requires a first number of MIPs to complete a first receive process for the first communication port, and a second number of MIPs to complete a first transmit process for the first communication port, and said DSP is adapted with sufficient processing power to handle both said first receive process and said first transmit process for at least said first communications port.

41. The system of claim 40 wherein said DSP is adapted with sufficient processing power to handle a second number of receive processes and a second number of transmit processes for a second number of communication ports, said second number of communication ports being based on a total number of MIPs achievable by said DSP.