Thinned die integrated circuit package

• US 6,841,413 B2
• Filed: 01/07/2002
• Issued: 01/11/2005
• Est. Priority Date: 01/07/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Liu, Cheng-Yi, Swan, Johanna
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US10/036,389
• Publication Number:
  US 20030127715A1
• Time in Patent Office: 1,100 Days
• Field of Search: 451/57, 257/712, 257/713, 257/778, 257/612, 257/714, 257/720, 257/722, 438/106
• US Class Current: 438/106
• CPC Class Codes: H01L 21/4871 Bases, plates or heatsinks
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/142 Metallic substrates having insulating layers
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/367 : Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A method and apparatus provide an integrated circuit package with improved heat dissipation and easier fabrication. The integrated circuit package includes a thinned semiconductor die attached to a heat spreader using a thermally conductive material. The thinned die reduces the thermal resistance of the die/heat spreader combination to improve heat extraction from the die as well as eliminating processing steps in fabrication. Additionally, the thinned die becomes more compliant as it takes on the thermal/mechanical properties of the heat spreader to reduce stress-induced cracking of the die.

Claims

1. A method of fabricating an integrated circuit package, comprising:

mounting a thinned semiconductor die on a planar surface of a heat spreader, wherein mounting includes attaching said die to the heat spreader by metal to metal diffusion bonding.

2. The method of claim 1, wherein mounting includes mounting said die on to the heat spreader using a thermally conductive material.

3. The method of claim 1, wherein said die has a thickness of no more than 100 μ

m.

4. The method of claim 1, wherein said die is made thin by at least one of plasma etching, grinding, polishing, and chemical etching.

5. A method of fabricating an integrated circuit package, comprising:

mounting a thinned semiconductor die on a planar surface of a heat spreader; and

forming at least one build-up layer over the die and heat spreader.

6. The method of claim 5, wherein forming includes emplacing a dielectric material to planarize exposed top surfaces of the heat spreader and the die.

7. The method of claim 6, wherein forming includes forming at least one build-up layer that includes at least one conductive trace contacting at least one contact on said die.

8. The method of claim 7, wherein forming includes forming at least two build-up layers, said at least two build-up layers including at least one dielectric layer disposed on at least a portion of the at least one conductive trace, and at least one second conductive trace extending through the at least one dielectric layer to contact the at least one conductive trace.

9. The method of claim 6, wherein forming a build-up layer includes emplacing the dielectric material by one of spin coating, curtain coating, slot coating, roll coating, squeegee application, or dry film lamination.

10. A method of fabricating an integrated circuit package, comprising:

mounting a thinned semiconductor die on a planar surface of a heat spreader; and

forming a metallization layer on said die.

11. A method of fabricating an integrated circuit package, comprising:

providing a planar heat spreader;

mounting a plurality of thinned semiconductor dice on to a planar surface of said heat spreader to form a plurality of conjoined microelectronic packages; and

singulating said plurality of conjoined microelectronic packages.

12. The method of claim 11, further including forming at least one build-up layer over top surfaces of the die and the heat spreader.

13. The method of claim 12, further including singulating said plurality of microelectronic packages by simultaneously cutting through said heat spreader and said at least one build-up layer.

14. The method of claim 12, further including forming a set of contacts to connect to an external component, the external component including a motherboard.

15. The method of claim 11, wherein mounting includes mounting the plurality of semiconductor dice on to the heat spreader using a thermally conductive material.

16. The method of claim 15, wherein mounting includes forming a diffusion bond.

17. The method of claim 11, wherein said die as a thickness of no more than 100 um.

18. A method of fabricating an integrated circuit package, comprising:

mounting a thinned semiconductor die on a planar surface of a heat spreader, wherein the thinned semiconductor die has a thickness of no more than 100 μ

m, and wherein mounting includes;

depositing a metallization layer on a back surface of the die.

19. The method according to claim 18, wherein the metallization layer includes a plurality of sublayers.

20. The method according to claim 18, wherein the metallization layer includes a plurality of sublayers, selected from titanium, nickel, vanadium, and tin;

titanium, nickel, vanadium, and gold; and

titanium, nickel, vanadium, an tin and gold.

21. The method according to claim 18, wherein mounting is carried out by thermal bonding.

22. The method according to claim 18, wherein mounting includes forming a diffusion bond.

23. The method according to claim 18, further including:

forming at least one build-up layer over the die and heat spreader.

24. The method according to claim 18, further including:

forming at least two build-up layers over the die and heat spreader.

25. The method according to claim 18, wherein the thinned semiconductor die is one of a plurality of thinned semiconductor dice mounted on the planar surface of said heat spreader to form a plurality of conjoined microelectronic packages.

26. The method according to claim 25, further including:

forming at least one build-up layer that includes a conductive trace contacting at least one contact on one of said dice.

27. The method according to claim 25, further including:

forming at least one build-up layer that includes a conductive trace contacting at least one contact on one of said dice; and

singulating said plurality of conjoined microelectronic packages.

28. The method according to claim 27, where singulating includes singulating said plurality of microelectronic packages by simultaneously cutting through said heat spreader and said at least one build-up layer.

29. The method according to claim 25, wherein mounting includes mounting the plurality of semiconductor dice on to the heat spreader using a thermally conductive material.

30. The method according to claim 25, wherein mounting includes forming a diffusion bond.