Chip-like electronic components, a method of manufacturing the same, a pseudo wafer therefor and a method of manufacturing thereof

• US 6,841,454 B2
• Filed: 08/09/2002
• Issued: 01/11/2005
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Nishiyama, Kazuo
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Mitchell, James M.
• Application Number:
  US10/216,508
• Publication Number:
  US 20020192867A1
• Time in Patent Office: 886 Days
• Field of Search: 438/458, 438/459, 438/460, 438/118, 438/106, 438/113, 438/110, 438/68
• US Class Current: 438/458
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05005 Structure
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In order to have a thin type semiconductor chips featuring a high yield and a low cost in production, an excellent packaging reliability, and a robust structure against damages, there is provided a method of manufacturing LSI chips, comprising the steps of: pasting on a substrate an adhesive sheet which retains its adhesive strength prior to a processing, then loses it after the processing; bonding non-defective LSI chips on the adhesive sheet, with their device surfaces facing downward; uniformly coating an insulating film on the non-defective LSI chips; uniformly grinding the insulating film to a level of the bottom surfaces of these LSI chips; applying a predetermined process to the adhesive sheet to weaken its adhesive strength thereof so as to peel off a pseudo wafer on which the non-defective LSI chips are bonded; and dicing the LSI chips into a discrete non-defective electronic component by cutting the pseudo wafer.

Claims

1. A method of manufacturing chip-like electronic components comprising the steps of:

pasting an adhesive material on a substrate, said adhesive material having a property to retain an adhesive strength prior to a processing and to lose said adhesive strength after said processing;

fixing a plurality of a same or different types of semiconductor chips on said adhesive material with an electrode surface thereof facing down;

coating a whole area including said plurality of the same or different types of semiconductor chips and a gap therebetween with a protective material;

removing said protective material from a side thereof opposite to said electrode surface to a level of a surface of the semiconductor chips;

applying a predetermined process to said adhesive material to weaken said adhesive strength of said adhesive material so as to peel off a pseudo wafer comprising said plurality of same or different types of semiconductor chips; and

dicing said plurality of the same or said different types of semiconductor chips into each semiconductor chip or each chip-like electronic component by cutting said protective material in said gap therebetween.

2. The method of manufacturing a chip-like electronic components according to claim 1, wherein:

said substrate has a flat surface;

said adhesive material is an adhesive sheet;

said plurality of the same or different types of semiconductor chips bonded on said adhesive sheet are non-defective;

said protective material is either one of an organic insulating material and an inorganic insulating material, and is uniformly coated on said semiconductor chips;

said protective material is uniformly ground to a level of the of said semiconductor chips;

said predetermined process includes irradiating ultraviolet rays on said adhesive sheet through said flat substrate from a bottom surface thereof opposite to the surface on which said plurality of semiconductor chips are bonded, or applying a chemical solution or heating the same to weaken said adhesive strength of said adhesive sheet so as to peel off a pseudo wafer having said plurality of the same or different types of semiconductor chips bonded integrally and covered with said protective material, from said flat substrate, said plurality of the same or different types of semiconductor chips bonded integrally on said pseudo wafer being totally non-defective and arrayed thereon with their electrode surfaces exposed; and

further

said pseudo wafer is diced between said plurality of the same or different types of semiconductor chips.

3. The method of manufacturing a chip-like electronic components according to claim 1, further comprising the steps of:

dicing said pseudo wafer at a position of said protective material between said plurality of the same or said plurality of different types of semiconductor chips; and

integrating a plurality of a same or different types of semiconductor chips to be mounted on a packaging substrate.

4. The method of manufacturing a chip-like electronic components according to claim 3, further comprising the step of forming solder bumps on said electrodes.

5. The method of manufacturing a chip-like electronic components according to claim 1, further comprising the step of bonding on said substrate said plurality of semiconductor chips which are determined to be non-defective in a characteristic measurement thereof.

6. The method of manufacturing a chip-like electronic components according to claim 1, further comprising the steps of:

carrying out said characteristic measurement on said plurality of semiconductor chips in a state they are bonded with said protective material; and

selecting non-defective semiconductor chips or non-defective chip-like electronic components.

7. The method of manufacturing chip-like electronic components according to claim 1 and further wherein the substrate is a solid material.

8. A method of manufacturing a pseudo wafer comprising the steps of:

pasting an adhesive material on a substrate, said material having a property to retain an adhesive strength prior to a processing and lose said adhesive strength after said processing;

bonding on said adhesive material a plurality of a same or different types of semiconductor chips with their electrode surfaces facing downward;

coating with a protective material a whole area of said plurality of the same or different types of semiconductor chips including a gap therebetween;

removing said protective material from a side opposite to said electrode surfaces to a level of the surfaces of the semiconductor chips; and

applying a predetermined process to said adhesive material to weaken its adhesive strength so as to peel off a pseudo wafer on which said plurality of the same or different types of semiconductor chips are bonded.

9. The method of manufacturing a pseudo wafer according to claim 8, wherein:

said substrate has a flat surface;

said adhesive material is an adhesive sheet;

said plurality of the same or different types of semiconductor chips bonded on said adhesive sheet with their electrode surfaces facing downward are non-defective;

said protective material is either one of an organic insulating resin or an inorganic insulating material functioning, and is uniformly coated on said semiconductor chips;

said protective material is uniformly ground to a level of surfaces of said semiconductor chips;

said predetermined process includes irradiating ultraviolet rays, through said substrate, on said adhesive sheet from a side thereof opposite to the surface thereof bonding said plurality of the same or different types of semiconductor chips thereon, or applying a chemical solution thereto or heating said adhesive sheet to weaken the adhesive strength of said adhesive sheet so as to peel off a pseudo wafer having said plurality of the same or different types of semiconductor chips bonded with said protection material from said substrate; and

thereby

said pseudo wafer having said plurality of the same or different types of non-defective semiconductor chips arrayed thereon, with their electrode surfaces exposed is obtained.

10. The method of manufacturing a pseudo wafer according to claim 8, further comprising the step of forming a solder bump on said electrode.

11. The method of manufacturing a pseudo wafer according to claim 8, further comprising the step of bonding on said substrate said semiconductor chips which are determined to be non-defective in characteristic measurements thereof.

12. The method of manufacturing a pseudo wafer according to claim 8, comprising the steps of:

carrying out a characteristic measurement on said semiconductor chips in a state as they are bonded with said protective material; and

selecting non-defective semiconductor chips or non-defective chip-like electronic components therefrom.

13. The method of manufacturing a pseudo-wafer according to claim 8, and further wherein the substrate is a solid material.