Semiconductor package and fabrication method thereof

• US 6,841,872 B1
• Filed: 11/13/2000
• Issued: 01/11/2005
• Est. Priority Date: 01/05/2000
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Jong-Hun, Ha, Seong-Kweon
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Farahani, Dana
• Application Number:
  US09/709,523
• Time in Patent Office: 1,520 Days
• Field of Search: 257/678, 257/692, 257/693, 257/697, 257/698, 257/773, 257/779, 257/780, 257/781, 257/782, 257/783, 257/784, 257/737, 257/738, 257/613, 257/620, 257/529, 257/668, 257/623, 257/696, 438/106
• US Class Current: 257/736
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]

Abstract

A semiconductor package and a fabrication method thereof can enhance adhesion between a solder and a package body by employing an irregular metal pattern, and improve stability. The semiconductor package includes a semiconductor substrate; a plurality of chip pads separately formed on an upper surface of the semiconductor substrate; an irregular metal pattern electrically connected to the plurality of chip pads; and an external terminal electrically connected to the metal pattern. In addition, a method of fabricating the semiconductor package includes the steps of separately forming a plurality of chip pads on an upper surface of a semiconductor substrate; forming an irregular metal pattern electrically connected to the plurality of chip pads; and forming an external terminal electrically connected to the metal of chip pads; and forming an external terminal electrically connected to the metal pattern.

Claims

1. A semiconductor package, comprising:

a semiconductor substrate;

a plurality of chip pads separately formed on an upper surface of the semiconductor substrate;

a first metal pattern formed on an upper surface of respective chip pads;

a second metal pattern formed on an upper surface of the first metal pattern and having a plurality of bulkheads separately formed on the first metal pattern, wherein a width of the bulkhead is uniform regardless of a height of the bulkhead; and

an external terminal electrically connected to an upper surface of the second metal pattern and a side portion of the bulkhead and extending into a space between the plurality of bulkheads.

2. The semiconductor package according to claim 1, wherein the first metal pattern includes titanium.

3. The semiconductor package according to claim 1, wherein the second metal pattern includes nickel.

4. The semiconductor package according to claim 1, further comprising:

a first insulation layer formed on a region of the upper surface of the semiconductor substrate not occupied by the plurality of chip pads; and

a second insulation layer formed on upper surfaces of the first insulation layer and the first metal pattern.

5. The semiconductor package according to claim 4, wherein the first insulation layer includes polymide or benzocyclobutene.

6. The semiconductor package according to claim 4, wherein the second insulation layer includes a photoresist layer or benzocyclobutene.

7. The semiconductor package according to claim 4, further comprising a solder mask formed on an upper surface of the second insulation layer.

8. The semiconductor package according to claim 4, wherein the external terminal includes a solder ball.

9. The semiconductor package according to claim 8, wherein the semiconductor substrate includes a wafer.