System and method for heterogeneous multi-site testing

• US 6,842,022 B2
• Filed: 09/20/2002
• Issued: 01/11/2005
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Khoche, Ajay
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US10/252,863
• Publication Number:
  US 20040059972A1
• Time in Patent Office: 844 Days
• Field of Search: 324/754, 324/765, 324/158.1, 324/72.5, 324/758, 324/763, 714/719, 714/720, 714/724, 714/119, 365/201, 438/14, 438 17- 19, 254/48
• US Class Current: 324/754.03
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371

Abstract

Disclosed are systems and methods which implement multi-site testing in which a test sequence implemented with respect to dice of a set of dice for parallel testing is not identical. Accordingly, heterogeneous test sequences are employed with respect to dice tested in parallel. A sequence of tests for testing individual circuit blocks of dice may be selected for optimizing the time for testing the set of dice for which parallel testing is conducted. Additionally or alternatively, a sequence of tests for testing individual circuit blocks of dice may be selected for managing and/or reducing the resources utilized in testing the dice. Moreover, test sequences may be dynamically determined for the dice of a set of dice being tested in parallel, such as in response to feedback provided by sensors monitoring the dice, to address various side effects.

Claims

1. A system for testing dice on a wafer, said system comprising:

automated test equipment having a plurality of test resources, wherein ones of said test resources perform different circuitry tests including a first circuitry test and a second circuitry test; and

a probe for placing said plurality of test resources in communication with a set of dice comprising a plurality of dice on said wafer, wherein control circuitry of said automated test equipment performs said first and second circuitry tests in a different order with respect to a first die and a second die of said set of dice.

2. The system of claim 1, wherein testing of said first die and said second die is performed concurrently using said different order of performing said first and second circuitry tests.

3. The system of claim 1, wherein said different order of said first and second circuitry tests is selected at least in part based upon a restriction with respect to simultaneous testing of said first and second die.

4. The system of claim 1, wherein said different order of said first and second circuitry tests is selected at least in part based upon a limitation with respect to a test resource of said plurality of test resources.

5. The system of claim 1, wherein said different order of said first and second circuitry tests is selected at least in part based upon an effect of testing of said first and second dice.

6. The system of claim 5, wherein said effect comprises a temperature.

7. The system of claim 5, wherein said effect comprises power consumption.

8. The system of claim 1, wherein said different order of said first and second circuitry tests is selected dynamically during testing of said dice on said wafer.

9. The system of claim 8, further comprising:

a sensor for monitoring an effect of testing of said first and second dice, wherein said dynamic selection of said different order of said first and second circuitry tests is based at least in part upon information provided by said sensor.

10. The system of claim 1, wherein said plurality of test resources comprises more than 2 test resources providing different types of tests.

11. The system of claim 1, wherein said set of dice comprises more than 2 dice of said plurality of dice.

12. The system of claim 1, wherein said first and second dice comprise circuitry in addition to circuitry associated with said first and second circuitry tests.

13. A method for testing blocks of circuitry on a wafer, said method comprising:

establishing heterogeneous test sequences for use in testing said blocks of circuitry; and

testing a plurality of said blocks of circuitry in parallel using said heterogeneous test sequences.

14. The method of claim 13, wherein said establishing heterogeneous test sequences comprises:

selecting an order of testing said blocks of circuitry based at least in part upon testing restrictions associated with said blocks tested in parallel.

15. The method of claim 13, wherein said establishing heterogeneous test sequences comprises:

selecting an order of testing said blocks of circuitry based at least in part upon limitations associated with test resources of an automated test equipment utilized in performing said testing.

16. The method of claim 13, wherein said establishing heterogeneous test sequences comprises:

selecting an order of testing said blocks of circuitry based at least in part upon an effect associated with said testing.

17. The method of claim 13, further comprising:

dynamically reconfiguring said heterogeneous test sequences after testing of said blocks of circuitry on said wafer has commenced.

18. The method of claim 17, wherein said reconfiguring said heterogeneous test sequences is based at least in part upon monitored attributes of said testing of said blocks of circuitry on said wafer.

19. The method of claim 18, wherein said testing said plurality of said blocks of circuitry in parallel comprises:

monitoring operational attributes of said plurality of blocks in addition to those being tested, wherein said reconfiguring said heterogeneous test sequence is based at least in part upon said monitored operational attributes.

20. The method of claim 13, wherein said establishing heterogeneous test sequences comprises:

optimizing a total time for testing said blocks of circuitry.

21. The method of claim 13, wherein said establishing heterogeneous test sequences comprises:

optimizing a number of test resources utilized in testing said blocks of circuitry.

23. The method of claim 13, wherein said first die and said second die comprise a same set of circuit blocks.

24. The method of claim 13, further comprising:

dynamically reestablishing at least one of said first test sequence and said second test sequence.

22. A method for testing dice on a wafer, said method comprising:

establishing a first test sequence for testing circuit blocks of a first die on said wafer;

establishing a second test sequence for testing circuit blocks of a second die on said wafer, wherein said first test sequence provides for testing of circuit blocks in a different order than does said second test sequence; and

testing said first die using said first test sequence while testing said second die using said second test sequence.