Low-to-high voltage conversion method and system

• US 6,842,046 B2
• Filed: 01/31/2002
• Issued: 01/11/2005
• Est. Priority Date: 01/31/2002
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Walker, William W., Tzartzanis, Nestor
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US10/066,355
• Publication Number:
  US 20030141899A1
• Time in Patent Office: 1,076 Days
• Field of Search: 326 93- 98, 326/62, 326/68, 326/81, 326/83, 326/119, 326/121
• US Class Current: 326/98
• CPC Class Codes: H03K 19/01855 synchronous, i.e. using clock signals

Abstract

A system and method, for converting a voltage input from a low voltage source to a voltage output at a high voltage source using a domino logic circuit design. An embodiment provides a low to high voltage conversion system. The system includes: a pull-up transistor coupled to a high voltage source for charging a node, when a precharge signal is received; a low voltage source used for setting an input voltage; a pull-down network for discharging the node depending, at least in part, on the input voltage; and an output voltage determined from the node.

Claims

1. A method for converting an input signal, comprising an input voltage from a low voltage source, to an output signal, comprising an output voltage from a high voltage source, by a digital circuit, comprising a pull-down logic network coupled to a node, the high voltage source having a voltage level greater than the low voltage source, said method comprising:

precharging said node to a high voltage using said high voltage source during a first period of time, said step including turning on a first transistor that is coupled between said high voltage source and said node;

turning off the first transistor during a subsequent second period of time;

receiving said input voltage from said low voltage source by said pull-down logic network;

determining a voltage of said node based on evaluating said pull-down logic network during the subsequent second period of time, the conductance between said node and said high voltage source being at the low level during the determination step; and

using said voltage of said node, determining said output voltage.

2. The method of claim 1 further comprising maintaining said high voltage on said node by a keeper circuit.

3. The method of claim 2 wherein said keeper circuit comprises a pMOS transistor.

4. The method of claim 1 further comprising disconnecting said pull-down logic network from ground during said precharging.

5. The method of claim 1 further comprising setting said input voltage to a low logic level voltage during said precharging.

6. The method of claim 1 further comprising setting said input voltage to near ground during said precharging.

7. The method of claim 1 wherein said determining said output voltage comprises a CMOS gate inputting said voltage of said node and generating said output voltage.

8. The method of claim 1 wherein during said evaluating said pull-down logic network, said input voltage is stable.

9. The method of claim 1 wherein the digital circuit further comprises a ground potential, and wherein said method further comprises the step of substantially isolating the node from the ground potential during the first period of time.

10. A low-to-high voltage conversion system, comprising:

a pull-up transistor coupled to a high voltage source for charging a node during a first period of time when a precharge signal is received, said pull-up transistor being turned-on during the first period of time and being turned-off during a subsequent second period of time;

a low voltage source used for setting an input voltage, wherein said low voltage source produces a voltage reference less than said high voltage source;

a pull-down network for discharging said node during the subsequent second period of time depending, at least in part, on said input voltage, said pull-up transistor being turned-off when said node is being discharged by the pull-down network; and

an output voltage determined from said node.

11. The low-to-high voltage conversion system of claim 10 wherein said output voltage comprises a high voltage from said high voltage source when said node is discharged.

12. The low-to-high voltage conversion system of claim 10 further comprising a keeper circuit for maintaining said node when charged, said keeper circuit comprising a pull up transistor.

13. The low-to-high voltage conversion system of claim 10 further comprising a foot switch for disconnecting said pull-down network when said precharged signal is received.

14. The low-to-high voltage conversion system of claim 13 wherein said foot switch comprises an nMOS transistor.

15. The low-to-high voltage conversion system of claim 10 wherein said output voltage is determined from said node using a CMOS gate.

16. The low-to-high voltage conversion system of claim 10 further comprising another input voltage set by using said low voltage source.

17. The low-to-high voltage conversion system of claim 16 wherein said pull down network is coupled to ground.

18. The low-to-high voltage conversion system of claim 17 wherein both said input voltage and said another input voltage are near ground when said precharge signal is received.

19. The low-to-high voltage conversion system of claim 10 wherein said voltage reference has a larger voltage range than a conventional low-to-high voltage converter circuit.

20. The low-to-high voltage conversion system of claim 10 wherein said input voltage comprises a voltage level above an effective threshold voltage of a transistor.

21. The low-to-high conversion system of claim 10 further comprising a ground potential, and wherein the node is substantially isolated from the ground potential during the first period of time.

22. A system for converting a first logic level at a low voltage to a second logic level at a high voltage, comprising:

a first terminal for receiving a high voltage source, said high voltage source having a value;

a second terminal for receiving a low voltage source which has a value less than the value of the high voltage source;

a pull-up transistor coupled to the high voltage source for charging a node during a first period of time when a precharge signal is at a low logic level, said pull-up transistor being turned-on during the first period of time and being turned-off during a subsequent second period of time when the precharge signal is at a high logic level;

an input signal, comprising an input voltage representing said first logic level, said input voltage set by using the low voltage source;

a pull-down network for discharging said node during the subsequent second period of time depending, at least in part, on said input voltage, said pull-up transistor being turned-off when said node is being discharged by the pull-down network;

a footer switch, comprising an nMOS transistor, and connecting said pull-down network to ground when said precharge signal is at the high logic level; and

a keeper circuit, comprising a pMOS transistor, for maintaining said node when charged; and

an output voltage determined from said node.

23. The system of claim 22 further comprising an additional input voltage set by using said low voltage source, wherein said pull-down network is further for discharging said node depending, at least in part, on said additional input voltage.

24. The system of claim 22 wherein the node is substantially isolated from the ground potential during the first period of time.

25. A low-to-high conversion system, comprising:

a first terminal for receiving a high voltage source, said high voltage source having a value;

a second terminal for receiving a low voltage source which has a value less than the value of the high voltage source;

circuitry generating an input signal from the low voltage source received at the second terminal;

means for precharging a node to a high voltage using the high voltage source received at the first terminal during a first period of time, said means for precharging the node including a first transistor that is turned on during the first period of time and turned off during a subsequent second period of time;

means for evaluating a voltage of said node based on said input voltage and a pull-down network during the subsequent second period of time, wherein said pull-down network has means for connecting said pull-down network to ground to discharge said node, the conductance between said node and said high voltage source being at the low level when the node is being discharged by the pull-down network; and

means for using said voltage of said node to determine said output voltage.

26. The system of claim 25 further comprising means for keeping said high voltage on said node.

27. The system of claim 25 wherein said system is used in a register file.

28. The system of claim 25 further comprising a third terminal for receiving a ground potential and means for substantially isolating the node from the ground potential during the first period of time.