Multi-level Class-D amplifier by means of 2 physical layers

• US 6,842,070 B2
• Filed: 06/30/2003
• Issued: 01/11/2005
• Est. Priority Date: 04/17/2003
• Status: Active Grant

• Current Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Original Assignee: Dialog Semiconductor GmbH (Renesas Electronics Corporation)
• Inventors: Nilsson, Johan
• Primary Examiner(s): Nguyen, Patricia
• Application Number:
  US10/610,046
• Publication Number:
  US 20040207465A1
• Time in Patent Office: 561 Days
• Field of Search: 330/10, 330/251, 330/207.A
• US Class Current: 330/10
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/2175 using analogue-digital or digital-analogue conversion H03F3/2173 takes precedence

Abstract

Introduce a pulse length control mechanism to generate virtual multi-level output pulses for a Class-D Amplifier, which has only 2 physical output levels. Typically a Sigma-Delta-Modulator converts the input signal into high frequency low bit rate. The disclosed invention adds functions to transform the SDM signal into pulses with equivalent multi-level time-voltage areas and adds a pulse-length-control mechanism to produce various output pulse patterns, where the summations of the positive and negative pulses, within one sampling period, result in time-voltage area values, corresponding to 3 or more digital levels. Thus the invention produces higher signal quality at lower sampling rates.

Claims

1. A circuit to generate virtual multi-level output pulses for a Class-D Amplifier with only 2 physical levels, where the resulting time-voltage-area corresponds to a multiple of digital levels, comprising:

means to convert the input signal into a PDM (Pulse Density Modulated) signal;

means to generate the output of said PDM (Pulse Density Modulated) as a signal, representing the desired multiple of pulse areas values;

means to determine the required length-ratio of positive and negative pulse portions within one sampling period, where said pulse length ratio represents said multiple pulse-area values;

means to define a set of output pulse-area values, one for each step of said multiple pulse-area values;

means to control the time of pulse phase changes within one sampling period;

a pulse generator providing the virtual multi-level output pulses to a power driver, using said pulse length controlled signal;

means for a Class-D power driver to drive voltage into an output load, controlled by said power driver pulses, typically a Complementary-Pair-Driver or an equivalent circuit; and

means for an output load as the amplifier'"'"'s output target.

2. The circuit of claim 1 wherein said input signal is an analog signal.

3. The circuit of claim 1 wherein said input signal is PCM (Pulse Code Modulated), i.e. a digital signal with low sampling rate and high bit resolution.

4. The circuit of claim 1 wherein said means to convert the input signal into a PDM (Pulse Density Modulated) signal comprises a Sigma Delta Modulator.

5. The circuit of claim 1 wherein said means to generate the output of said PDM (Pulse Density Modulated) as a signal, representing the desired multiple of pulse areas values is implemented in a digital signal processor as an integrated part together with the Sigma Delta Modulator.

6. The circuit of claim 1 wherein said means to determine said pulse length ratio can provide at least 3 values.

7. The circuit of claim 1 wherein said means to control said pulse length ratio uses a system provided clock signal, to define the start of the first portion of the driving pulse.

8. The circuit of claim 1 wherein said means to control said pulse length ratio produces a change-phase-signal between clock pulses, defining the end of the first pulse portion and defining the start of the second pulse portion.

9. The circuit of claim 8 wherein said means to determine the change-phase-time is a time integrating function.

10. The circuit of claim 9 where said time integrating function to determine the change-phase-time is implemented within a “

Length of Pulse Integrator”

unit.

11. The circuit of claim 1 wherein said means to define a set of output pulse-area values assumes a set of fixed and a priori known magnitudes.

12. The circuit of claim 11 wherein said set of a priori known magnitudes, representing said set of output pulse-area values, can be varied by means of an external control definition.

13. The circuit of claim 1 wherein said means for a Class-D power driver is a Complementary Driver Pair (Half-Bridge).

14. The circuit of claim 1 wherein said means to convert said PDM (Pulse Density Modulated) signal is implemented as an integrated digital logic function.

15. The circuit of claim 1 wherein said means to convert said PDM (Pulse Density Modulated) signal is implemented as a calculating algorithm in a digital signal processor.

16. The circuit of claim 1 wherein said means to control said pulse length ratio, representing said multiple pulse-area values, is implemented as an integrated digital logic function.

17. The circuit of claim 1 wherein said means to control said pulse length ratio, representing said multiple pulse-area values is implemented as a calculating algorithm in a digital signal processor.

18. The circuit of claim 9 wherein said time integrating function to determine said change-phase-time, is implemented as an analog integrated function.

19. The circuit of claim 9 wherein said time integrating function to determine said change-phase-time, is implemented as an integrated digital logic function.

20. The circuit of claim 9 wherein said time integrating function to determine said change-phase-time, is implemented as a calculating algorithm in a digital signal processor.

21. The circuit of claim 1 wherein said pulse generator providing said virtual multi-level output pulses for said power driver is implemented as an integrated digital logic function.

22. The circuit of claim 1 wherein said pulse generator providing said virtual multi-level output pulses for said power driver is implemented as a calculating algorithm in a digital signal processor.

23. A method to generate virtual multi-level output pulses for a Class-D Amplifier with only 2 physical levels, where the resulting time-voltage-area corresponds to a multiple of digital levels, comprising:

providing means to convert the input signal into ideal PDM (Pulse Density Modulated) control pulses, means to generate the output of said PDM (Pulse Density Modulated) converter as a signal, representing the desired multiple of values of pulse areas, means to define a set of output pulse-area values, means to determine the required length-ratio of positive and negative pulse portions within a sampling period, means to control the time of pulse phase changes, a pulse generator providing the virtual multi-level output pulses to a power driver, means for a Class-D power driver to drive voltage into an output load and means for an output load;

converting said input signal into ideal PDM (Pulse Density Modulated) control pulses;

generating the output of said PDM signal converter as a multiple of values, representing the desired pulse areas;

determining said length-ratio of positive and negative pulse portions within one sampling period, where said pulse length ratio represents said multiple pulse-area values;

defining a set of output pulse-area values, one for each step of said multiple pulse-area values;

controlling the time to change the pulse phase within a sampling period, based on the desired pulse length ratio, with an appropriate time control mechanism;

generating said virtual multi-level output pulses under control of the signal, which changes said pulse phase;

applying said virtual multi-level output pulses to said Class-D power driver; and

driving said power driver'"'"'s output voltage to the output load (typically a loudspeaker).

24. The method of claim 23 wherein converting said input signal into ideal PDM control pulses is done by a processing unit containing a Sigma Delta Modulator.

25. The method of claim 23 wherein converting said input signal into ideal PDM control pulses and generating the output of said PDM signal as a signal, representing the desired multiple of values of pulse areas, is performed within a combined function.

26. The method of claim 23 wherein controlling said pulse length ratio uses 3 or more values.

27. The method of claim 23 wherein controlling said time to change the pulse phases, starts one phase of said pulses at a system provided clock signal, typically the sampling clock of the PDM signal.

28. The method of claim 23 wherein controlling said time to change the pulse phases, alternates the pulse phase at a time primarily depending on the required pulse length ratio, and in direct relation to said system provided clock signal, typically the sampling clock of the PDM signal.

29. The method of claim 28 wherein determining the time to alternate said pulse phase is performed by integrating the time and comparing the result with a value derived from said pulse length ratio.

30. The method of claim 29 wherein determining the time to alternate said pulse phase by integrating the time and comparing the result with a value derived from said pulse length ratio, is done in a “

Length of Pulse Integrator”

function.

31. The method of claim 23 wherein defining the set of output pulse area references assumes a set of fixed and a priori known magnitudes.

32. The method of claim 23 wherein an external control definition can vary said set of a priori known magnitudes, which represent said set of output pulse-area values.

33. The method of claim 23 wherein a Complementary Driver Pair (Half-Bridge) is used for driving voltage to said output load.

34. The method of claim 23 wherein converting said input signal into ideal PDM power driver control pulses is implemented by an integrated digital logic function.

35. The method of claim 23 wherein converting said input signal into ideal PDM power driver control pulses is implemented by a calculating algorithm in a digital signal processor.

36. The method of claim 23 wherein controlling said pulse length ratio, representing said multiple pulse-area values, is implemented by an integrated digital logic function.

37. The method of claim 23 wherein controlling said pulse length ratio, representing said multiple pulse-area values is implemented by a calculating algorithm in a digital signal processor.

38. The method of claim 23 wherein the time integrating function, determining the time to change the pulse phase within a sampling period is partially implemented by an integrated analog function.

39. The method of claim 23 wherein controlling the time to change the pulse phase within a sampling period, based on the desired pulse length ratio is implemented by an integrated digital logic function.

40. The method of claim 23 wherein controlling the time to change the pulse phase within a sampling period, based on the desired pulse length ratio is implemented by a calculating algorithm in a digital signal processor.

41. The method of claim 23 wherein generating said multi-level power driver control pulses is performed in an integrated digital logic function.

42. The method of claim 23 wherein generating said multi-level power driver control pulses is performed in a calculating algorithm in a digital signal processor.