Low-jitter clock distribution circuit
First Claim
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1. A low-jitter clock distribution circuit, comprising:
- a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor, the channel lengths of the P-channel and N-channel transistors in each inverter being substantially equal, the ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter being equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by a semiconductor fabrication process by which the clock distribution circuit is manufactured.
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Abstract
A low-jitter clock distribution circuit, used in an integrated circuit having multiple analog-to-digital converters (ADCs), includes a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor. The ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter is equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by the semiconductor fabrication process.
12 Citations
8 Claims
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1. A low-jitter clock distribution circuit, comprising:
a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor, the channel lengths of the P-channel and N-channel transistors in each inverter being substantially equal, the ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter being equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by a semiconductor fabrication process by which the clock distribution circuit is manufactured. - View Dependent Claims (2)
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3. A multiple-channel analog-to-digital converter integrated circuit, comprising:
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a plurality of analog-to-digital converters, each analog-to-digital converter having a clock input for receiving a sampling clock; and
a clock distribution circuit for distributing a clock signal to the clock input of the analog-to-digital converters, the clock distribution circuit including a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor, the channel lengths of the P-channel and N-channel transistors in each inverter being substantially equal, the ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter being equal to substantially the square root of the ratio Un/Up of the majority carrier mobilities of the N-channel and P-channel transistors as determined by a semiconductor fabrication process by which the integrated circuit is manufactured. - View Dependent Claims (4, 8)
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5. A low-jitter clock distribution circuit, comprising:
a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor, the channel lengths Lp and Ln of the P-channel and N-channel transistors in each inverter being unequal, the N-channel and P-channel transistors having a ratio Un/Up of majority carrier mobilities as determined by a semiconductor fabrication process by which the clock distribution circuit is manufactured, the ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter being equal to substantially the square root of (Un/Up*Lp/Ln*(A*Ln+1)/(A*Lp+1)), where A is a parameter determined by the semiconductor process. - View Dependent Claims (6)
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7. A multiple-channel analog-to-digital converter integrated circuit, comprising:
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a plurality of analog-to-digital converters, each analog-to-digital converter having a clock input for receiving a sampling clock; and
a clock distribution circuit for distributing a clock signal to the clock input of the analog-to-digital converters, the clock distribution circuit including a plurality of cascaded inverters, each inverter including an upper P-channel transistor connected to a lower N-channel transistor, the channel lengths Lp and Ln of the P-channel and N-channel transistors in each inverter being unequal, the N-channel and P-channel transistors having a ratio Un/Up of majority carrier mobilities as determined by a semiconductor fabrication process by which the integrated circuit is manufactured, the ratio Wp/Wn of the widths of the P-channel and N-channel transistors in each inverter being equal to substantially the square root of (Un/Up*Lp/Ln*(A*Ln+1)/(A*Lp+1)), where A is a parameter determined by the semiconductor process.
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Specification
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsAgarwal, Nitin, Rath, Shakti Shankar
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Primary Examiner(s)YOUNG, BRIAN K
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Application NumberUS10/724,296Time in Patent Office410 DaysField of Search341/155, 341/144, 341/136, 713/500US Class Current341/155CPC Class CodesG06F 1/10 Distribution of clock signa...H03M 1/0863 of switching transients, e....H03M 1/1215 using time-division multipl...H03M 1/123 Simultaneous, i.e. using on...
