High-density content addressable memory cell

• US 6,842,360 B1
• Filed: 05/30/2003
• Issued: 01/11/2005
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Netlogic Microsystems Incorporated (Broadcom, Inc.)
• Inventors: Srinivasan, Varadarajan
• Primary Examiner(s): Lam, David
• Application Number:
  US10/452,230
• Time in Patent Office: 592 Days
• Field of Search: 365/49, 365/189.07, 365/177, 365/104, 711/108
• US Class Current: 365/49.1
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

A content addressable memory (CAM) cell. The CAM cell includes a first and second memory cells and a diffusion region. First and second transistors are formed adjacent one another in the diffusion region and coupled to the first memory cell, and third and fourth transistors are formed adjacent one another in the diffusion region and coupled to the second memory cell.

Claims

1. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell; and

a compare circuit, the compare circuit including;

a first diffusion region,

first and second transistors formed adjacent one another in the first diffusion region and each coupled to the first memory cell, and

third and fourth transistors formed adjacent one another in the first diffusion region and each coupled to the second memory cell.

2. The CAM cell of claim 1 wherein the first and second transistors are formed by a first polysilicon feature extending from the first memory cell to the first diffusion region.

3. The CAM cell of claim 1 further comprising a reference contact disposed on the first diffusion region between the first and second transistors.

4. The CAM cell of claim 1 further comparing a first match line contact disposed on the diffusion region between the second transistor and the third transistor, and second and third match line contacts disposed on the diffusion region at opposite ends of the CAM cell, the first match line contact being coupled to a first match line, and the second and third match line contacts being coupled to a second match line.

5. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell;

a first diffusion region;

a first compare circuit coupled to a first match line and having a first transistor formed in the first diffusion region and coupled to the first memory cell, and a second transistor formed in the first diffusion region and coupled to the second memory cell; and

a second compare circuit coupled to a second match line and having a first transistor formed in the first diffusion region and coupled to the first memory cell and a second transistor formed in the first diffusion region and coupled to the second memory cell.

6. The CAM cell of claim 5 wherein channels of the first and second transistors of the first compare circuit are formed by respective portions of the first diffusion region.

7. The CAM cell of claim 5 further comprising a first continuous feature that extends over a first area of the first diffusion region and a second area of the first diffusion region to form the first and second transistors, respectively, of the first compare circuit.

8. The CAM cell of claim 7 wherein the first continuous feature is a polysilicon feature.

9. The CAM cell of claim 7 further comprising a second continuous feature that extends over a third area of the first diffusion region and a fourth area of the first diffusion region to form the first and second transistors, respectively, of the second compare circuit.

10. The CAM cell of claim 5 wherein the first memory cell comprises a second diffusion region, and wherein the first continuous feature further extends over the second diffusion region.

11. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell;

a first compare circuit coupled to a first match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell;

a second compare circuit coupled to a second match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell;

a first layer of conductive material including a conductive structure coupled between the first transistor of the first compare circuit and the first memory cell; and

a second layer of conductive material including a conductive structure coupled between the second transistor of the first compare circuit and the second memory cell.

12. The CAM cell of claim 11 further comprising an insulating layer disposed between the first and second layers of conductive material, and wherein the conductive structure disposed in the first layer of conductive material overlaps the conductive structure disposed in the second layer of conductive material.

13. The CAM cell of claim 11 wherein the first layer of conductive material is a first metal layer, and wherein the second layer of conductive material is a second metal layer.

14. The CAM cell of claim 13 wherein the conductive structure disposed in the first layer of conductive material is a metal trace formed in the first metal layer.

15. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell;

a first compare circuit coupled to a first match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell;

a second compare circuit coupled to a second match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell; and

a first layer of conductive material, the first transistor of the first compare circuit and the first transistor of the second compare circuit being coupled to the first memory cell through the first layer of conductive material, and the second transistor of the first compare circuit and the second transistor of the second compare circuit being coupled to the second memory cell through the first layer of conductive material.

16. The CAM cell of claim 15 wherein the first layer of conductive material comprises a layer of polysilicon.

17. The CAM cell of claim 15 wherein the first layer of conductive material comprises a layer of metal.

18. The CAM cell of claim 15 further comprising an insulating layer disposed on the first layer of conductive material and a second layer of conductive material disposed on the insulating layer.

19. A content addressable memory (CAM) cell comprising:

a first memory cell;

a second memory cell;

a diffusion region;

a first compare circuit formed at least in part on the diffusion region, the first compare circuit being coupled to a first match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell;

a second compare circuit formed at least in part on the diffusion region, the second compare circuit being coupled to a second match line and having a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell;

a first contact disposed on the diffusion region and coupled to the first match line and to a first portion of the first compare circuit; and

a second contact disposed on the diffusion region and coupled to the first match line and to a second portion of the first compare circuit.

20. The CAM cell of claim 19 wherein the first portion of the first compare circuit includes the first transistor of the first compare circuit, and wherein the second portion of the first compare circuit includes the second transistor of the first compare circuit.

21. The CAM cell of claim 19 wherein the diffusion region extends between opposite boundaries of the CAM cell, and wherein the first and second contacts are disposed at the opposite boundaries of the CAM cell.

22. The CAM cell of claim 19 wherein the first contact is coupled between the first match line and the first portion of the compare circuit.

23. The CAM cell of claim 19 wherein the first and second contacts are disposed at opposite sides of the CAM cell, and wherein the CAM cell further comprises a third contact coupled to the second match line and disposed on the diffusion region substantially midway between the opposite sides.

24. A content addressable memory (CAM) cell comprising:

a diffusion feature having non-overlapping first, second and third regions, the first region being disposed between the second and third regions;

a first compare circuit disposed within the first region; and

a second compare circuit having a first compare sub-circuit disposed in the second region and a second compare sub-circuit disposed in the third region.

25. The CAM cell of claim 24 further comprising first and second memory cells coupled to the first and second compare circuits.

26. The CAM cell of claim 25 wherein the first compare circuit comprises a first transistor coupled to the first memory cell and a second transistor coupled to the second memory cell.

27. The CAM cell of claim 26 wherein the first sub compare circuit comprises a first transistor coupled to the first memory cell, and wherein the second sub-compare circuit comprises a first transistor coupled to the second memory cell.

28. The CAM cell of claim 27 wherein the first compare circuit further comprises a third transistor coupled to a first compare line, and a fourth transistor coupled to a second compare line.

29. The CAM cell of claim 28 wherein the first sub-compare circuit further comprises a second transistor coupled to a third compare line, and wherein the second sub-compare circuit further comprises a second transistor coupled to a fourth compare line.

30. The CAM cell of claim 25 wherein the first compare circuit is coupled to the first memory cell and to the second memory cell, the first compare sub-circuit is coupled to the first memory cell, and the second sub-compare circuit is coupled to the second memory cell.

31. The CAM cell of claim 30 wherein the first compare circuit is coupled to first and second compare lines, the first sub-compare circuit is coupled to a third compare line, and the second sub-compare circuit is coupled to a fourth compare line.

32. The CAM cell of claim 30 wherein the first compare circuit is coupled to first and second compare lines to receive a first complementary pair of comparand signals, and wherein the first and second sub-compare circuits are coupled to third and fourth compare lines, respectively, to receive a second complementary pair of comparand signals within the second compare circuit.

33. A content addressable memory (CAM) device comprising:

a row of N CAM cells including a diffusion region that extends across each of the N CAM cells, N first contacts disposed on the diffusion region, and N+1 second contacts disposed on the diffusion region;

a first match line coupled to each of the N first contacts; and

a second match line coupled to each of the N+1 second contacts.

34. The CAM device of claim 33 wherein each of the N first contacts is disposed between opposing boundaries of a respective one of the N CAM cells.

35. The CAM device of claim 33 wherein the row of N CAM cells comprises N+1 boundaries including a pair of boundaries at opposite ends of the row, and N−

1 boundaries between the N CAM cells, and wherein the N+1 second contacts are disposed respectively at the N+1 boundaries.

36. The CAM device of claim 35 wherein each of the N contacts is disposed between a respective pair of the N+1 contacts.