Intermesh memory device
First Claim
Patent Images
1. An intermesh memory device, comprising:
- memory components each configured to have a determinable resistance value, the memory components formed as a first memory array with a first set of the memory components and formed as a second memory array with a second set of the memory components, the first and second memory arrays each having rows of the memory components substantially perpendicular to columns of the memory components such that the first memory array rows and columns of the memory components are interconnected with the second memory array rows and columns of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components; and
wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.
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Abstract
An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.
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Citations
59 Claims
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1. An intermesh memory device, comprising:
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memory components each configured to have a determinable resistance value, the memory components formed as a first memory array with a first set of the memory components and formed as a second memory array with a second set of the memory components, the first and second memory arrays each having rows of the memory components substantially perpendicular to columns of the memory components such that the first memory array rows and columns of the memory components are interconnected with the second memory array rows and columns of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components; and
wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component. - View Dependent Claims (2, 3, 5, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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4. An intermesh memory device comprising:
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memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components;
wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component; and
wherein the memory components form a first region and the electronic switches form a second region, the first region offset from the second region and the first region substantially parallel to the second region.
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6. An intermesh memory device, comprising:
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memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components;
wherein a first electronic switch is electrically coupled to drive an input of a first memory component and a second electronic switch is electrically coupled to sense an output of the first memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the first memory component; and
wherein the first electronic switch is electrically coupled to drive an input of at least a second memory component and a third electronic switch is electrically coupled to sense an output of the second memory component, the first electronic switch and the third electronic switch configured together to apply a potential to the second memory component.
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8. An intermesh memory device, comprising:
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memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components, wherein a first set of the electronic switches are p-channel field effect transistors and wherein a second set of the electronic switches are n-channel field effect transistors; and
wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.
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9. An intermesh memory device, comprising:
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memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;
electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components; and
wherein a first electronic switch is an n-channel field effect transistor electrically coupled to drive an input of a memory component and a second electronic switch is a p-channel field effect transistor electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.
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21. An electrical structure, comprising:
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electronic switches fabricated in a semiconductive material on a semiconductor substrate;
electrically resistive components fabricated in a device region offset from the semiconductive material, the electrically resistive components configured to form an intermesh array of memory cells formed with a first set of the electrically resistive components intersected by a second set of the electrically resistive components; and
electrically conductive vias each configured to electrically couple one or more of the electronic switches to an electrically resistive component of the first set and to an electrically resistive component of the second set. - View Dependent Claims (22, 23, 24, 25, 28, 29, 30, 31)
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26. An electrical structure, comprising:
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electronic switches fabricated in a semiconductive material on a semiconductor substrate, the electronic switches including a first set of p-channel field effect transistors and a second set of n-channel field effect transistors;
electrically resistive components fabricated in a device region offset from the semiconductive material, the electrically resistive components configured to form an intermesh array of memory cells formed with a first set of the electrically resistive components intersected by a second set of the electrically resistive components; and
electrically conductive vias configured to electrically couple one or more of the electronic switches to one or more of the electrically resistive components.
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27. An electrical structure, comprising:
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electronic switches fabricated in a semiconductive material on a semiconductor substrate, the electronic switches configured as an array of voltage controlled switches, the array including p-channel field effect transistors alternating with n-channel field effect transistors;
electrically resistive components fabricated in a device region offset from the semiconductive material, the electrically resistive components configured to form an intermesh array of memory cells formed with a first set of the electrically resistive components intersected by a second set of the electrically resistive components; and
electrically conductive vias configured to electrically couple one or more of the electronic switches to one or more of the electrically resistive components.
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32. A method, comprising:
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forming electronic switches on a semiconductor substrate;
forming electrically conductive vias; and
forming memory components in an intermesh array that includes a first set of the memory components and includes a second set of the memory components, the first set of the memory components being substantially perpendicular to the second set of the memory components such that the first set of the memory components are interconnected with the second set of the memory components, a first set memory component being electrically coupled to a first electronic switch with a first electrically conductive via and the first set memory component being electrically coupled to a second electronic switch with a second electrically conductive via, and a second set memory component being electrically coupled to the second electronic switch with the second electrically conductive via and the second set memory component being electrically coupled to a third electronic switch with a third electrically conductive via. - View Dependent Claims (33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48)
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37. A method comprising:
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forming electronic switches as alternating p-channel field effect transistors and n-channel field effect transistors on a semiconductor substrate;
forming electrically conductive vias;
forming memory components in an intermesh array, an individual memory component being electrically coupled to a first electronic switch with a first electrically conductive via and the individual memory component being electrically coupled to a second electronic switch with a second electrically conductive via.
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49. An electronic device, comprising:
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means for applying a drive voltage with a drive pillar coupled to drive an input of a first memory component in an intermesh memory device;
means for applying a sense voltage with a sense pillar coupled to sense an output of the first memory component; and
means for sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar are enabled. - View Dependent Claims (50)
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51. An electronic device, comprising:
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means for enabling a first electronic switch coupled to apply a drive voltage to an input of a first memory component in a first array of memory components in an intermesh memory device;
means for enabling a second electronic switch coupled to apply a sense voltage to an output of the first memory component;
means for sensing a resistance value of the first memory component, the resistance value being determinable when the first electronic switch and the second electronic switch are enabled;
means for enabling the first electronic switch coupled to apply the drive voltage to an input of a second memory component in a second array of memory components in the intermesh device;
means for enabling a third electronic switch coupled to apply a second sense voltage to an output of the second memory component; and
means for sensing a resistance value of the second memory component, the resistance value being determinable when the first electronic switch and the third electronic switch are enabled.
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52. An electronic device, comprising:
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means for enabling a first electronic switch coupled to apply a drive voltage to an input of a row memory component in an intermesh memory device;
means for enabling a second electronic switch coupled to apply a sense voltage to an output of the row memory component; and
means for sensing a resistance value of the row memory component, the resistance value being determinable when the first electronic switch and the second electronic switch are enabled;
means for enabling the first electronic switch coupled to apply a drive voltage to an input of a column memory component in the intermesh memory device;
means for enabling a third electronic switch coupled to apply a sense voltage to an output of the column memory component; and
means for sensing a resistance value of the column memory component, the resistance value being determinable when the first electronic switch and the third electronic switch are enabled.
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53. A method, comprising:
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applying a first voltage to an input of a first memory component in an intermesh memory device, the first voltage being applied with a drive pillar coupled to the input of the first memory component;
applying a second voltage to an output of the first memory component, the second voltage being applied with a sense pillar coupled to the output of the first memory component; and
sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar apply a potential to the first memory component. - View Dependent Claims (54, 55, 56, 57, 58, 59)
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Specification