Internal voltage generating circuit for periphery, semiconductor memory device having the circuit and method thereof

• US 6,842,382 B2
• Filed: 08/12/2002
• Issued: 01/11/2005
• Est. Priority Date: 08/14/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jae-Hoon, Youn, Jae-Youn
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US10/217,799
• Publication Number:
  US 20030035325A1
• Time in Patent Office: 883 Days
• Field of Search: 365/189.09, 365/226, 365/203, 365/207, 327/546
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address. The internal voltage can be supplied only to peripheral circuits of the banks selected by the bank address, thereby preventing unnecessary power consumption, effectively controlling the internal voltage, and always properly supplying the internal voltage.

Claims

1. An internal voltage generator comprising:

a switchable internal voltage generating circuit having a reference voltage input and an internal voltage output, the internal voltage generating circuit maintaining the internal voltage output equal to the reference voltage when switched on; and

a control section to switch on the internal voltage generating circuit in response to a bank activation command and a bank activation signal.

2. The internal voltage generator of claim 1, wherein the bank activation signal is generated in response to a bank address.

3. The internal voltage generator of claim 1, wherein the control section switches the internal voltage generating circuit on only when both the bank activation command and the bank activation signal are enabled.

4. The internal voltage generator of claim 3, wherein the control section comprises a NAND means for performing an AND operation of the bank activation command and the bank activation signal and inverting the result, and an inverter for inverting the output of the NAND means, the inverter supplying a control signal to the internal voltage generating circuit.

5. The internal voltage generator of claim 1, wherein the control section switches the internal voltage generating circuit on when either the bank activation command or the bank activation signal is enabled.

6. The internal voltage generator of claim 5, wherein when both the bank activation command and the bank activation signal are enabled, the internal voltage generating circuit supports a larger range of drive currents at the internal voltage output than it supports with only one of the bank activation command and the bank activation signal enabled.

7. The internal voltage generator of claim 5, wherein the control section comprises first and second MOS transistors connected to the internal voltage generating circuit as parallel current sinks, the bank activation command applied to the gate of the first MOS transistor, the bank activation signal applied to the gate of the second MOS transistor.

8. The internal voltage generator of claim 1, wherein the internal voltage generating circuit comprises a differential amplifier with one differential input connected to the reference voltage input and the other differential input connected to the internal voltage output.

9. The internal voltage generator of claim 1, further comprising a level converter to precharge the internal voltage generating circuit when the internal voltage generating circuit is switched off.

10. The internal voltage generator of claim 1, incorporated into a semiconductor memory device comprising multiple such internal voltage generators and a plurality of memory banks to store data, each bank comprising memory cells and peripheral circuitry, wherein the internal voltage generator is connected to supply an internal voltage to the peripheral circuitry of a corresponding on of the memory banks in response to the bank activation command, the bank activation signal corresponding to that memory bank.

11. The internal voltage generator of claim 1, wherein the switchable internal voltage generating circuit comprises:

a current mirror;

a switchable current source to allow current to flow through the current mirror in response to the bank activation signal and the bank activation command; and

a differential amplifier connected between the current mirror and the switchable current source, the differential amplifier maintaining the internal voltage output equal to the reference voltage when the switchable current source is switched on.

12. The internal voltage generator of claim 11, wherein the current mirror comprises first and second MOS transistors having common sources connected to an external voltage, and common gates connected to the drain of the second MOS transistor;

and

the differential amplifier comprises third, fourth, and fifth MOS transistors, the third and fourth MOS transistors having common sources connected to the current source, the third MOS transistor having a gate connected to the reference voltage and a drain connected to the first MOS transistor drain, the fourth MOS transistor having a gate connected to the internal voltage output and a drain connected to the second MOS transistor drain, the fifth MOS transistor having a gate connected to the first MOS transistor drain, a source connected to the external voltage, and a drain connected to the internal voltage output.

13. The internal voltage generator of claim 12, wherein, the switchable current source comprises a sixth MOS transistor having a gate connected to a control signal that is asserted when both the bank activation signal and the bank activation command are asserted.

14. The internal voltage generator of claim 12, wherein, the switchable current source comprises sixth and seventh MOS transistors having common drains and sources, the sixth MOS transistor having a gate coupled to the bank activation command, the seventh MOS transistor having a gate coupled to the bank activation signal.

15. The internal voltage generator of claim 12, further comprising a level converter to precharge that internal voltage generating circuit.

16. An internal voltage generator comprising:

a switchable internal voltage generating circuit having a reference voltage input and an internal voltage output, the internal voltage generating circuit maintaining the internal voltage output equal to the reference voltage when switched on; and

a control section to switch on the internal voltage generating circuit in response to a bank activation command and a first bank activation signal selected from among a plurality of bank activation signals, the control section not switching on the internal voltage generating circuit in response to another of the bank activation signals.

17. The internal voltage generator of claim 16, wherein the first bank activation signal is generated in response to a bank address.

18. The internal voltage generator of claim 16, wherein the control section switches the internal voltage generating circuit on only when both the first bank activation command and the bank activation signal are enabled.

19. The internal voltage generator of claim 18, wherein the control section comprises a NAND means for performing an AND operation of the bank activation command and the first bank activation signal and inverting the result, and an inverter for inverting the output of the NAND means, the inverter supplying a control signal to the internal voltage generating circuit.

20. The internal voltage generator of claim 16, wherein the control section switches the internal voltage generating circuit on when either the bank activation command or the first bank activation signal is enabled.

21. The internal voltage generator of claim 20, wherein when both the bank activation command and the first bank activation signal are enabled, the internal voltage generating circuit supports a larger range of drive currents at the internal voltage output than it supports with only one of the bank activation command and the first bank activation signal enabled.

22. The internal voltage generator of claim 20, wherein the control section comprises first and second MOS transistors connected to the internal voltage generating circuit as parallel current sinks, the bank activation command applied to the gate of the first MOS transistor, the first bank activation signal applied to the gate of the second MOS transistor.

23. The internal voltage generator of claim 16, wherein the internal voltage generating circuit comprises a differential amplifier with one differential input connected to the reference voltage input and the other differential input connected to the internal voltage output.

24. The internal voltage generator of claim 16, further comprising a level converter to precharge the internal voltage generating circuit when the internal voltage generating circuit is switched off.

25. The internal voltage generator of claim 16, incorporated into a semiconductor memory device comprising multiple such internal voltage generators and a plurality of memory banks to store data, each bank comprising memory cells and peripheral circuitry, wherein the internal voltage generator is connected to supply an internal voltage to the peripheral circuitry of a corresponding on of the memory banks in response to the bank activation command, the first bank activation signal corresponding to that memory bank.

26. The internal voltage generator of claim 16, wherein the switchable internal voltage generating circuit comprises:

a current mirror;

a switchable current source to allow current to flow through the current mirror in response to the first bank activation signal and the bank activation command; and

a differential amplifier connected between the current mirror and the switchable current source, the differential amplifier maintaining the internal voltage output equal to the reference voltage when the switchable current source is switched on.

27. The internal voltage generator of claim 26, wherein the current mirror comprises first and second MOS transistors having common sources connected to an external voltage, and common gates connected to the drain of the second MOS transistor;

and

the differential amplifier comprises third, fourth, and fifth MOS transistors, the third and fourth MOS transistors having common sources connected to the current source, the third MOS transistor having a gate connected to the reference voltage and a drain connected to the first MOS transistor drain, the fourth MOS transistor having a gate connected to the internal voltage output and a drain connected to the second MOS transistor drain, the fifth MOS transistor having a gate connected to the first MOS transistor drain, a source connected to the external voltage, and a drain connected to the internal voltage output.

28. The internal voltage generator of claim 27, wherein, the switchable current source comprises a sixth MOS transistor having a gate connected to a control signal that is asserted when both the first bank activation signal and the bank activation command are asserted.

29. The internal voltage generator of claim 27, wherein, the switchable current source comprises sixth and seventh MOS transistors having common drains and sources, the sixth MOS transistor having a gate coupled to the bank activation command, the seventh MOS transistor having a gate coupled to the first bank activation signal.

30. The internal voltage generator of claim 27, further comprising a level converter to precharge that internal voltage generating circuit.