Method and apparatus for interference cancellation in a rake receiver

• US 6,842,479 B2
• Filed: 11/05/2001
• Issued: 01/11/2005
• Est. Priority Date: 10/02/1998
• Status: Expired due to Term

• Current Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Bottomley, Gregory E.
• Primary Examiner(s): Ghebretinsae, Temesghen
• Application Number:
  US09/992,094
• Publication Number:
  US 20020051485A1
• Time in Patent Office: 1,163 Days
• Field of Search: 375/130, 375/147, 375/150, 375/343, 375/148
• US Class Current: 375/150
• CPC Class Codes: H04B 1/7095 Sliding correlator type
• CPC Class Codes: H04B 1/7113 Determination of path profile
• CPC Class Codes: H04B 1/712 Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 25/0328 with interference cancellation circuitry adaptations for interference cancellation within a sequence estimator H04L25/03305; interference related aspects of direct sequence spread spectrum H04B1/7097; interference related aspects of frequency hopping spread spectrum H04B1/715; see also H04B1/10
• CPC Class Codes: H04L 25/03299 with noise-whitening circuitry
• CPC Class Codes: H04L 25/03337 Arrangements involving per-survivor processing

Abstract

Systems and methods for despreading received spread spectrum signals are described. Despreading can be performed using both channel estimates and impairment correlation estimates. Techniques for selecting delays of interest are also described, along with a despreading mechanism which saves power by operating only on delays of interest.

Claims

1. A sliding correlator comprising:

a delay line having a plurality of delay elements for delaying a stream of data samples input thereto;

a plurality of remove chip units, each associated with an output of one of said plurality of delay elements, for removing chips from said delayed data samples;

an adder for receiving outputs from said plurality of remove chip units and adding said outputs together; and

an inhibit unit for selectively enabling at least one of said plurality of remove chip units and said adder.

2. The sliding correlator of claim 1, wherein said delay line is a circular buffer.

3. The sliding correlator of claim 1, wherein said inhibit unit operates to enable said at least one of said plurality of remove chip units and said adder only for delays of interest.

4. The sliding correlator of claim 1, wherein said inhibit unit selectively enables and disables said plurality of remove chip units and said adder together.