Apparatus for emulation of electronic systems

• US 6,842,729 B2
• Filed: 03/26/2002
• Issued: 01/11/2005
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Sample, Stephen P., D'Amour, Michael R., Payne, Thomas S.
• Primary Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US10/107,741
• Publication Number:
  US 20020107682A1
• Time in Patent Office: 1,022 Days
• Field of Search: 703/24, 716/6, 371/21.2, 371/21.4, 371/21.5, 371/22.2, 371/28, 340/825.83, 340/825.84, 340/825.86, 340/825.87, 340/825.79, 326 36- 38, 326/40, 326/41, 326/44, 326/45, 326/47, 365/94, 365/103, 365/104, 365/154, 365/189.07, 365/189.08, 365/201, 702/118, 702/119, 714/725
• US Class Current: 703/24
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user'"'"'s circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Claims

1. A hardware logic emulation system capable of implementing a digital logic design, said digital logic design comprised of combinational and sequential logic elements, comprising:

a printed circuit board;

an array of programmable gate array devices arranged in a matrix on said printed circuit boards, each of said programmable gate array devices adapted to implement a portion of said digital logic design, and each of said programmable gate array devices comprising a plurality of input/output pins;

a plurality of input/output pin conductors, each of said plurality of input/output pin conductors forming a part of said printed circuit board and wherein at least some of said input/output pin conductors are placed in electrical communications with at least some of said input/output pins on each of said programmable gate array devices such that at least some of said input/output pins on said programmable gate array devices are placed in direct electrical communication with other of said programmable gate array devices;

a computer adapted to receive input data representative of said digital logic design and to process said input data into a form that can be implemented in said plurality of programmable gate array devices.

2. The hardware logic emulation system of claim 1 wherein said plurality of programmable integrated circuits comprise identical types of programmable gate array devices.

3. The hardware logic emulation system of claim 1 wherein said computer runs a partitioning program which determines which of said programmable gate array devices are capable of being reserved for interconnecting others of said programmable gate array devices.