Fabrication method of nitride-based semiconductors and nitride-based semiconductor fabricated thereby

• US 6,844,569 B1
• Filed: 04/26/2004
• Issued: 01/18/2005
• Est. Priority Date: 12/20/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Lee, Kyu Han, Kim, Sun Woon, Kim, Je Won
• Primary Examiner(s): Everhart, Caridad
• Assistant Examiner(s): Yevsikov, Victor V
• Application Number:
  US10/831,190
• Time in Patent Office: 267 Days
• Field of Search: 257/79, 257/94, 257/89, 257/200, 257/103, 257/96, 257/97, 257/99, 438/46, 438/47
• US Class Current: 257/79
• CPC Class Codes: C30B 29/605 Products containing multiple oriented crystallites, e.g. columnar crystallites
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

The present invention relates to a fabrication method of nitride-based semiconductors and a nitride-based semiconductor fabricated thereby. In the fabrication method of the invention, a self-organizing metal layer is formed on a sapphire substrate. The sapphire substrate having the self-organizing metal layer is heated so that self-organizing metal coalesces into nanoscale clusters to irregularly expose an upper surface of the sapphire substrate. Exposed portions of the sapphire substrate is plasma etched using the self-organized metal clusters as a mask to form a nanoscale uneven structure on the sapphire substrate. A resultant structure is wet etched to remove the self-organized metal clusters. The nanoscale uneven structure formed on the sapphire substrate decreases the stress and resultant dislocation between the sapphire substrate and a nitride-based semiconductor layer as well as increases the quantum efficiency between the same.

Claims

1. A fabrication method of nitride-based semiconductors comprising the following steps of:

(a) forming a self-organizing metal layer on a sapphire substrate;

(b) heating the sapphire substrate having the self-organizing metal layer so that self-organizing metal coalesces into nanoscale clusters to irregularly expose an upper surface of the sapphire substrate;

(c) plasma etching exposed portions of the sapphire substrate using the self-organized metal clusters as a mask to form a nanoscale uneven structure on the sapphire substrate; and

(d) wet etching a resultant structure to remove the self-organized metal clusters.

2. The fabrication method of nitride-based semiconductors according to claim 1, wherein the step (a) forms the self-organizing metal layer at a thickness of about 10 to 200 nm.

3. The fabrication method of nitride-based semiconductors according to claim 1, wherein the step (a) forms the self-organizing metal layer at a thickness of about 30 to 100 nm.

4. The fabrication method of nitride-based semiconductors according to claim 1, wherein the step (a) forms the self-organizing metal layer via vapor deposition.

5. The fabrication method of nitride-based semiconductors according to claim 4, wherein the vapor deposition is carried out via electron beam evaporation which generates electron beams at a voltage of about 5 kV and a discharge current of about 2 mA between a filament and a furnace in an electron beam pocket for a time period of about 5 to 10 minutes.

6. The fabrication method of nitride-based semiconductors according to claim 1, wherein the self-organizing metal layer is made of at least one selected from a group including Pt, Au, Cr and alloys thereof.

7. The fabrication method of nitride-based semiconductors according to claim 1, wherein the heating step (b) is carried out at a temperature range of about 500 to 1000°

C. in nitrogen atmosphere for about 2 to 10 mins.

8. The fabrication method of nitride-based semiconductors according to claim 1, wherein the heating step (b) is carried out at a temperature range of 700 to 1000°

C. in nitrogen atmosphere for about 7 to 10 mins.

9. The fabrication method of nitride-based semiconductors according to claim 1, wherein the etching step (c) is carried out via Inductive Coupled Plasma-Reactive Ion Etching (ICP-RIE).

10. The fabrication method of nitride-based semiconductors according to claim 9, wherein the ICP-RIE is carried out at a high frequency power of about 50 to 100W and a DC bias of about 100 to 300V under a pressure of about 1 to 100 mmTorr for about 5 to 20 min. while injecting HBr or BCl₃ at a flow rate of about 1 to 200 cc per min.

11. The fabrication method of nitride-based semiconductors according to claim 1, wherein the etching step (c) forms irregular-shaped pores in the exposed portions on the sapphire substrate, the pores having a width of about 50 to 500 nm and a depth of about 3 to 50 nm.

12. The fabrication method of nitride-based semiconductors according to claim 1, wherein the etching step (c) forms irregular-shaped pores in the exposed portions on the sapphire substrate, the pores having a width of about 50 to 500 nm and a depth of about 5 to 20 nm.

13. The fabrication method of nitride-based semiconductors according to claim 1, wherein the wet etching step (d) comprises:

immersing the etched sapphire substrate into aqua regia and heating the aqua regia containing the sapphire substrate at a temperature of about 80 to 90°

C. for about 30 secs. to 2 mins.

14. The fabrication method of nitride-based semiconductors according to claim 1, further comprising the step of forming a nitride layer on the sapphire substrate after the wet etching step (d).

15. The fabrication method of nitride-based semiconductors according to claim 1, wherein the sapphire substrate is replaced by one selected from a group including a SiC substrate, an oxide substrate and a carbide substrate.

16. A nitride-based semiconductor comprising:

a sapphire substrate;

a nitride nucleation layer, an n-doped GaN layer, an activation layer and a p-doped GaN layer formed in their order on the sapphire substrate; and

a nanoscale uneven structure formed on the sapphire substrate according to the method described in claim 1.

17. The nitride-based semiconductor according to claim 16, wherein the nanoscale uneven structure includes irregular-shaped pores having a width of about 50 to 500 nm and a depth of about 3 to 50 nm.

18. The nitride-based semiconductor according to claim 16, wherein the nanoscale uneven structure includes irregular-shaped pores having a width of about 50 to 500 nm and a depth of about to 20 nm.

19. The nitride-based semiconductor according to claim 16, wherein the sapphire substrate is replaced by one selected from a group including a SiC substrate, an oxide substrate and a carbide substrate.

20. A nitride-based semiconductor for use with a light emitting diode comprising:

a sapphire substrate;

a nitride nucleation layer, an n-doped GaN layer, an activation layer and a p-doped GaN layer formed in their order on the sapphire substrate; and

an uneven structure of irregular-shaped pores formed on the sapphire substrate, wherein the pores have a width of about 50 to 500 nm and a depth of about 3 to 50 nm.

21. The nitride-based semiconductor according to claim 20, wherein the pores have a width of about 50 to 500 nm and a depth of about 5 to 20 nm.