CMOS imager with a self-aligned buried contact

• US 6,844,580 B2
• Filed: 02/11/2003
• Issued: 01/18/2005
• Est. Priority Date: 06/18/1999
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Rhodes, Howard E.
• Primary Examiner(s): Nhu, David
• Application Number:
  US10/361,710
• Publication Number:
  US 20030148570A1
• Time in Patent Office: 707 Days
• Field of Search: 257/291, 257/231, 257/232, 257/233, 257/234, 257/292, 257/293, 257/288, 257/910
• US Class Current: 257/291
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14636 Interconnect structures

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Claims

1. An imaging device comprising:

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said photosensitive area;

a floating diffusion region in said substrate for receiving photo-generated charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate; and

,

a buried contact for interconnecting said floating diffusion region with said output transistor.

2. The imaging device according to claim 1, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

3. The imaging device according to claim 1, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

4. The imaging device according to claim 1, wherein said photosensitive area is a photodiode.

5. The imaging device according to claim 1, further including a charge transfer region between said photosensitive area and said floating diffusion region, said charge transfer region including a field effect transistor, wherein said buried contact is aligned to a gate structure of said field effect transistor.

6. The imaging device according to claim 5, wherein said output transistor is a source follower transistor and wherein said buried contact connects said floating diffusion region and said source follower transistor via interconnectors.

7. The imaging device according to claim 6, wherein said interconnectors are formed at least in part of doped polysilicon.

8. The imaging device according to claim 6, wherein said interconnectors are formed of at least one refractory metal.

9. The imaging device according to claim 8, wherein said refractory metal is tungsten.

10. The imaging device according to claim 6, wherein said interconnectors are formed of aluminum-copper alloy.

11. The imaging device according to claim 6, wherein said interconnectors are formed of copper.

12. The imaging device according to claim 8, wherein said refractory metal is titanium.

13. The imaging device according to claim 6 wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

14. The imaging device according to claim 6, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

15. The imaging device according to claim 6, wherein said photosensitive area is a photodiode.

16. The imaging device according to claim 5, further comprising an insulating layer formed over the gate of said transfer transistor and said source follower transistor and under the buried contact.

17. The imaging device according to claim 16, wherein said insulating layer includes a nitride.

18. The imaging device according to claim 16, wherein said insulating layer includes an oxide.

19. The imaging device according to claim 17, wherein said insulating layer is a nitride, ONO, NO, ON, or combinations thereof.

20. An imaging device comprising

a semiconductor integrated circuit substrate;

a photosensitive device formed on said substrate for accumulating photo-generated charge in an underlying region of said substrate;

a floating diffusion region in said substrate for receiving said photo-generated charge;

a readout circuit comprising at least an output transistor formed in said substrate; and

said floating diffusion region being connected to said output by a buried contact via interconnectors.

21. The imaging device according to claim 20, wherein said photosensitive device is a photogate.

22. The imaging device according to claim 20, wherein said photosensitive device is a photodiode.

23. The imaging device according to claim 20, wherein said photosensitive device is a photoconductor.

24. The imaging device according to claim 20, further including a charge transfer region between said photosensitive area and said floating diffusion region, said charge transfer region including a field effect transistor, wherein said buried contact is aligned to said field effect transistor.

25. The imaging device according to claim 24, wherein said output transistor is a source follower transistor and wherein said buried contact contacts said floating diffusion region and said source follower transistor via interconnectors.

26. The imaging device according to claim 25, wherein said interconnectors are formed at least in part of doped polysilicon.

27. The imaging device according to claim 25, wherein said interconnectors are formed of at least one refractory metal.

28. The imaging device according to claim 25, wherein said interconnectors are formed of aluminum-copper alloy.

29. The imaging device according to claim 25, wherein said interconnectors are formed of copper.

30. The imaging device according to claim 27, wherein said refractory metal is tungsten.

31. The imaging device according to claim 27, wherein said refractory metal is titanium.

32. The imaging device according to claim 24, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

33. The imaging device according to claim 24, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

34. The imaging device according to claim 24, wherein said photosensitive area is a photodiode.

35. The imaging device according to claim 20, wherein said output transistor is formed adjacent to said floating diffusion region on said substrate.

36. The imaging device according to claim 20, further comprising a reset transistor for resetting said floating diffusion region to a predetermined voltage.

37. The imaging device according to claim 20, wherein said floating diffusion region is an n-doped region in a p-well.

38. The imaging device according to claim 33, wherein said photogate is formed of doped polysilicon.

39. The imaging device according to claim 34, further comprising a lightly n-doped region beneath said photodiode.

40. The imaging device according to claim 21, further comprising an insulating layer formed over the gate of said transfer transistor and said source follower transistor and under the buried contact.

41. The imaging device according to claim 40, wherein said insulating layer includes a nitride.

42. The imaging device according to claim 40, wherein said insulating layer includes an oxide.

43. The imaging device according to claim 41, wherein said insulating layer is selected from the group consisting of a nitride, ONO, NO, ON, and combinations thereof.

44. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said photosensitive area;

a floating diffusion region in said substrate for receiving photo-generated charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate; and

,

a buried contact for interconnecting said floating diffusion region with said output transistor.

45. The system according to claim 44, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

46. The system according to claim 44, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

47. The system according to claim 44, wherein said photosensitive area is a photodiode.

48. The system according to claim 44, further including a charge transfer region between said photosensitive area and said floating diffusion region, said charge transfer region including a field effect transistor, wherein said buried contact is aligned to said field effect transistor.

49. The system according to claim 48, wherein said output transistor is a source follower transistor and wherein said buried contact contacts said floating diffusion region and said source follower transistor via interconnectors.

50. The system according to claim 49, wherein said interconnectors are formed at least in part of doped polysilicon.

51. The system according to claim 49, wherein said interconnectors are formed of at least one refractory metal.

52. The system according to claim 49, wherein said interconnectors are formed of aluminum copper alloy.

53. The system according to claim 49, wherein said interconnectors are formed of copper.

54. The system according to claim 51, wherein said refractory metal is tungsten.

55. The system according to claim 51, wherein said refractory metal is titanium.

56. The system according to claim 48, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

57. The system according to claim 48, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

58. The system according to claim 48, wherein said photosensitive area is a photodiode.

59. The system according to claim 48, further comprising an insulating layer formed over the gate of said transfer transistor and said source follower transistor and under the buried contact.

60. The system according to claim 59, wherein said insulating layer includes a nitride.

61. The system according to claim 59, wherein said insulating layer includes an oxide.

62. The system according to claim 60, wherein said insulating layer is a nitride, ONO, NO, ON, or combinations thereof.

63. An imaging device comprising:

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate; and

,

a buried contact formed over a doped region in said substrate and between two structures on said substrate for electrically connecting said imaging device, wherein said structures are selected from a transistor gate and an isolation region.

64. The imaging device according to claim 63, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

65. The imaging device according to claim 63, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

66. The imaging device according to claim 63, wherein said photosensitive area is a photodiode.

67. The imaging device according to claim 63, further including a charge transfer transistor and a reset transistor, wherein said buried contact is aligned between said transfer transistor and said reset transistor.

68. The imaging device according to claim 67, wherein said buried contact electrically connects said imaging device via interconnectors.

69. The imaging device according to claim 67, wherein said interconnectors are formed at least in part of doped polysilicon.

70. The imaging device according to claim 67, wherein said interconnectors are formed of at least one refractory metal.

71. The imaging device according to claim 68, wherein said interconnectors are formed of an aluminum-copper alloy.

72. The imaging device according to claim 68, wherein said interconnectors are formed of copper.

73. The imaging device according to claim 70, wherein said refractory metal is tungsten.

74. The imaging device according to claim 70, wherein said refractory metal is titanium.

75. The imaging device according to claim 63, wherein said buried contact is formed between two transistor gates.

76. The imaging device according to claim 63, wherein said buried contact is formed between two isolation regions.

77. The imaging device according to claim 63, wherein said buried contact is formed between a transistor gate and an isolation region.

78. The imaging device according to claim 75, further comprising an insulating layer formed over the gate of said transistors and under the buried contact.

79. The imaging device according to claim 78, wherein said insulating layer includes a nitride.

80. The imaging device according to claim 78, wherein said insulating layer includes an oxide.

81. The imaging device according to claim 68, wherein said insulating layer is a nitride, ONO, NO, ON, or combinations thereof.

82. The imaging device according to claim 74, wherein said isolation region is a field oxide region.

83. The imaging device according to claim 63, wherein said substrate is a semiconductor integrated circuit substrate.

84. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photo-generated charge in said photosensitive area;

a readout circuit comprising at least an output transistor formed on said substrate; and

,

a buried contact formed over a doped region in said substrate and between two structures on said substrate electrically connecting said imaging device, wherein said structures are selected from a transistor gate and an isolation region.

85. The system according to claim 84, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

86. The system according to claim 84, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

87. The system according to claim 84, wherein said photosensitive area is a photodiode.

88. The system according to claim 84, further including a charge transfer transistor and a reset transistor, wherein said buried contact is aligned between the gates of said charge transfer transistor and said reset transistor.

89. The system according to claim 88, wherein said buried contact electrically connects said imaging device via interconnectors.

90. The system according to claim 89, wherein said interconnectors are formed at least in part of doped polysilicon.

91. The system according to claim 89, wherein said interconnectors are formed of at least one refractory metal.

92. The system according to claim 91, wherein said refractory metal is tungsten.

93. The system according to claim 91, wherein said refractory metal is titanium.

94. The system according to claim 84, wherein said buried contact is formed between two transistor gates.

95. The system according to claim 84, wherein said buried contact is formed between two isolation regions.

96. The system according to claim 84, wherein said buried contact is formed between a transistor gate and an isolation region.

97. The system according to claim 84, further comprising an insulating layer formed over the gate of said transistors and under the buried contact.

98. The system according to claim 97, wherein said insulating layer includes a nitride.

99. The system according to claim 97, wherein said insulating layer includes an oxide.

100. The system according to claim 97, wherein said insulating layer is a nitride, ONO, NO, ON, or combinations thereof.

101. The system according to claim 95, wherein said isolation region is a field oxide region.

102. The system according to claim 84, wherein said substrate is a semiconductor integrated circuit substrate.