Semiconductor device with super junction region

• US 6,844,592 B2
• Filed: 03/17/2003
• Issued: 01/18/2005
• Est. Priority Date: 03/18/2002
• Status: Expired

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Masakazu, Omura, Ichiro, Saito, Wataru, Izumisawa, Masaru
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): Trinh, Hoa B.
• Application Number:
  US10/388,498
• Publication Number:
  US 20030222327A1
• Time in Patent Office: 673 Days
• Field of Search: 257/330, 257/331, 257/341, 257/343, 257/328, 257/327, 257/133, 257/139
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor device includes a first-conductivity-type semiconductor layer which includes a cell region portion and a junction terminating region portion. The junction terminating region portion is a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field.

Claims

1. A semiconductor device comprising:

a first—

first conductivity type semiconductor layer which includes a cell region portion and a junction terminating region portion, said junction terminating region portion being a region portion which is positioned in an outer periphery of the cell region portion to maintain a breakdown voltage by extending a depletion layer to attenuate an electric field;

a second-first conductivity type semiconductor layer which is formed on one surface of the first—

first conductivity type semiconductor layer;

a first main electrode which is electrically connected to the second-first conductivity type semiconductor layer;

first-second conductivity type semiconductor layers which are formed in the cell region portion of the first—

first conductivity type semiconductor layer in substantially vertical directions to said one surface of the first—

first conductivity type semiconductor layer, respectively, and which are periodically disposed in a first direction which is an arbitrary direction parallel to said one surface;

a second—

second conductivity type semiconductor layer which is selectively formed in the other surface portion of the first—

first conductivity type semiconductor layer so as to contact the first-second conductivity type semiconductor layers;

a third-first conductivity type semiconductor layer which is selectively formed in the surface portion of the second—

second conductivity type semiconductor layer;

a second main electrode which is formed so as to contact the second—

second conductivity type semiconductor layer and the third-first conductivity type semiconductor layer;

a control electrode which is formed on the surface of the first—

first conductivity type semiconductor layer sandwiched by the adjacent second—

second conductivity type semiconductor layers, the surface of the adjacent second—

second conductivity type semiconductor layers and the surface of the third-first conductivity type semiconductor layer, with a gate insulating film interposed therebetween; and

third-second conductivity type semiconductor layers which are formed in the junction terminating region portion and are periodically disposed in at least one direction of the first direction and a second direction perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein the third-second conductivity type semiconductor layers are respectively formed in a direction which is substantially perpendicular to said one surface of the first—

first conductivity type semiconductor layer.

3. The semiconductor device according to claim 1, wherein the third second conductivity type semiconductor layers are formed so as to have a polygonal or circular cross-sectional shape.

4. The semiconductor device according to claim 1, wherein at least one of the first-second conductivity type semiconductor layers and the third-second conductivity type semiconductor layers has a polygonal or circular plane shape.

5. The semiconductor device according to claim 1, wherein the first-second conductivity type semiconductor layers and the third-second conductivity type semiconductor layers have a stripe-shaped plane shape.

6. The semiconductor device according to claim 1, which further comprises an insulating film which is formed in at least any of the first-second conductivity type semiconductor layer, the third-second conductivity type semiconductor layer, a region portion of the first—

first conductivity type semiconductor layers which region portion is sandwiched by the first-second conductivity type semiconductor layers, a region portion of the first—

first conductivity type semiconductor layer which region portion is sandwiched by the third-second conductivity type semiconductor layers, a boundary surface between the first-second conductivity type semiconductor layers and the first—

first conductivity type semiconductor layer, and a boundary surface between the third-second conductivity type semiconductor layers and the first—

first conductivity type semiconductor layer.

7. The semiconductor device according to claim 6, wherein said insulating film has a stripe-shaped plane shape.

8. The semiconductor device according to claim 7, wherein said insulating films are positioned so as to be separated from one another at predetermined intervals.

9. The semiconductor device according to claim 1, wherein, assuming that an impurity amount of the third-second conductivity type semiconductor layers is N1 and that an impurity amount of the first-second conductivity type semiconductor layers is N2, N1 is greater than N2.

10. The semiconductor device according to claim 9, wherein the ratio N1/N2 of the impurity amount N1 of the third-second conductivity type semiconductor layers and the impurity amount N2 of the first-second conductivity type semiconductor layers satisfies the following expression:

1<

N1/N2<

1.63.

11. The semiconductor device according to claim 1, wherein, assuming that an arrangement interval of the third-second conductivity type semiconductor layers is CP1 and that an arrangement interval of the first-second conductivity type semiconductor layers is CP2, CP1 is narrower than CP2.

12. The semiconductor device according to claim 11, wherein the ratio CP2/CP1 of the arrangement interval CP1 of the third-second conductivity type semiconductor layers and the arrangement interval CP2 of the first-second conductivity type semiconductor layers satisfies the following expression:

1<

CP2/CP1<

2,

13. The semiconductor device according to claim 1, wherein the first—

first conductivity type semiconductor layer is formed such that an impurity concentration in said junction terminating region portion is lower than an impurity concentration in the cell region portion.

14. The semiconductor device according to claim 1, which further comprises a fourth-first conductivity type semiconductor layer which is provided between the first—

first conductivity type semiconductor layer and the second-first conductivity type semiconductor layer, the impurity concentration of the fourth-first conductivity type semiconductor layer being lower than that of the first—

first conductivity type semiconductor layer.

15. The semiconductor device according to claim 1, which further comprises a fourth-second conductivity type semiconductor layer which is formed in the vicinity of a boundary with the cell region portion in said junction terminating region portion so as to surround the cell region portion and which is connected to the first main electrode and the second main electrode.

16. The semiconductor device according to claim 1, which further comprises a junction terminating structure including a field plate electrode which is provided on the first—

first conductivity type semiconductor layer in said junction terminating region portion with an insulating film interposed therebetween.

17. The semiconductor device according to claim 1, which further comprises a junction terminating structure including a resurf layer which is formed in surface portions of the first—

first conductivity type semiconductor layer and of the third-second conductivity type semiconductor layers in said junction terminating region portion.

18. The semiconductor device according to claim 1, which further comprises a junction terminating structure including a plurality of guard ring layers which are formed in surface portions of the first—

first conductivity type semiconductor layer in said junction terminating region portion, or in surface portions of the first—

first conductivity type semiconductor layer and of the third-second conductivity type semiconductor layers.