Dielectric layer for semiconductor device and method of manufacturing the same

• US 6,844,604 B2
• Filed: 02/02/2001
• Issued: 01/18/2005
• Est. Priority Date: 02/02/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jongho, Lee, Nae-In
• Primary Examiner(s): WILLE, DOUGLAS A
• Application Number:
  US09/776,059
• Publication Number:
  US 20020106536A1
• Time in Patent Office: 1,446 Days
• Field of Search: 257/410
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS

Abstract

A multi-layer dielectric layer structure for a semiconductor device. The multi-layer dielectric layer structure comprises a silicate interface layer having a dielectric constant greater than that of silicon nitride and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises one or more ordered pairs of first and second layers. With the present invention, the dielectric constant of the high-k dielectric layer can be optimized while improving interface characteristics. With a higher crystallization temperature realized by forming the multi-layer structure, each of whose layers is not more than the critical thickness, leakage current can be reduced, thereby improving device performance.

Claims

1. A multi-layer structure for a semiconductor device, comprising:

a silicate interface layer; and

a high-k dielectric layer overlying the silicate interface layer, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.

2. The multi-layer structure of claim 1, wherein the silicate interface layer has a dielectric constant greater than that of silicon nitride.

3. The multi-layer structure of claim 1, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂).

4. The multi-layer structure of claim 3, wherein x is approximately 0.30-0.99.

5. The multi-layer structure of claim 3, wherein the metal “

M”

is selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

6. The multi-layer structure of claim 1, wherein the silicate interface layer is formed by an ALD technique, a MOCVD technique or a reactive sputtering technique.

7. The multi-layer structure of claim 1, wherein the silicate interface layer is formed to a thickness of approximately 5-10 angstroms.

8. The multi-layer structure of claim 1, wherein the high-k dielectric layer is a metal oxide layer.

9. The multi-layer structure of claim 8, wherein the metal oxide layer is an HfO₂ layer, a ZrO₂ layer, a Ta₂O₃ layer, an Al₂O₃ layer, a TiO₂ layer, an Y₂O₃ layer, or a BST layer, a PZT layer, or combinations thereof.

10. The multi-layer structure of claim 8, wherein the metal oxide layer is formed using an ALD technique, a MOCVD technique or a reactive sputtering technique.

11. The multi-layer structure of claim 8, wherein the silicate interface layer is formed of a metal silicate material, and wherein the metal of the silicate interface layer is the same as the metal of the metal oxide layer.

12. The multi-layer structure of claim 1, wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers.

13. The multi-layer structure of claim 12, wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or ZrO₂ and the second layer is formed of Al₂O₃.

14. The multi-layer structure of claim 12, wherein the first layer has a first fixed charge and the second layer has a second fixed charge opposite that of the first fixed charge.

15. The multi-layer structure of claim 12, wherein the thickness of the second layer is approximately one half the thickness of the first layer.

16. The multi-layer structure of claim 15, wherein the first layer is formed to a thickness of approximately 10 angstroms and the second layer is formed to a thickness of approximately 5 angstroms.

17. The multi-layer structure of claim 12, wherein a total thickness of the second layer is not more than approximately one third of the total thickness of the high-k dielectric layer.

18. The multi-layer structure of claim 12, wherein the upper most layer of the high-k dielectric layer is Al₂O₃.

29. The multi-layer structure of claim 1, wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.

30. The multi-layer structure of claim 13, wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.

19. A multi-layer structure for a semiconductor device, comprising:

a silicate interface layer having a dielectric constant greater than that of silicon nitride; and

a high-k dielectric layer overlying the silicate interface layer,

wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.

20. The multi-layer structure of claim 19, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂), the metal “

M”

being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

21. The multi-layer structure of claim 19, wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or ZrO₂ and the second layer is formed of Al₂O₃.

22. The multi-layer structure of claim 19, wherein the thickness of the second layer is approximately one half the thickness of the first layer.

23. The multi-layer structure of claim 19, wherein a total thickness of the second layer is not more than approximately one third of the total thickness of the high-k dielectric layer.

24. The multi-layer structure of claim 19, wherein the upper most layer of the high-k dielectric layer is Al₂O₃.

31. The multi-layer structure of claim 19, wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.

32. The multi-layer structure of claim 21, wherein the multi-layer is used for a capacitor between a lower electrode and an upper electrode.

25. A transistor comprising:

a substrate;

a silicate interface layer formed over the substrate; and

a high-k dielectric layer formed over the silicate interface layer;

a gate formed over the high-k dielectric layer; and

a source/drain region formed adjacent the gate, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.

26. The transistor of claim 25, wherein an upper most portion of the high-k dielectric layer is Al₂O₃, and wherein said gate comprises poly-silicon.

33. The transistor of claim 25, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂), the metal “

M”

being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

34. The transistor of claim 25, wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or Zro₂ and the second layer is formed of Al₂O₃.

27. A non-volatile memory, comprising:

a substrate;

a floating gate overlying the substrate;

a silicate interface layer formed over the floating gate;

a high-k dielectric layer formed over the silicate interface layer; and

a control gate overlying the high-k dielectric layer, wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.

35. The non-volatile memory of claim 27, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂), the metal “

M”

being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

36. The non-volatile memory of claim 27, wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or Zro₂ and the second layer is formed of Al₂O₃.

28. A capacitor for a semiconductor device, comprising;

a lower electrode;

a silicate interface layer formed over the lower electrode;

a high-k dielectric layer formed over the silicate interface layer; and

an upper electrode formed over the high-k dielectric layer wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer.

37. The capacitor of claim 28, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂), the metal “

M”

being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

38. The capacitor of claim 28, wherein the high-k

dielectric layer comprises one or more ordered pairs of first and second layers, and, wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or Zro₂ and the second layer is formed of Al₂O₃.

39. A capacitor, comprising:

a lower electrode;

a silicate interface layer having a dielectric constant greater than that of silicon nitride;

a high-k dielectric layer overlying the silicate interface layer,

wherein the high-k dielectric layer comprises one or more ordered pairs of first and second layers, and wherein the high-k dielectric layer has a dielectric constant greater than that of the silicate interface layer; and

an upper electrode.

40. The capacitor of claim 39, wherein the silicate interface layer is formed of a metal silicate material (M_1-xSi_xO₂), the metal “

M”

being selected from the group consisting of hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti) and aluminum (Al).

41. The capacitor of claim 39, wherein the first layer is formed of HfO₂, Ta₂O₃, Y₂O₃ or ZrO₂ and the second layer is formed of Al₂O₃.