Semiconductor device having a bond pad and method therefor

• US 6,844,631 B2
• Filed: 03/13/2002
• Issued: 01/18/2005
• Est. Priority Date: 03/13/2002
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Dinh, Dieu Van, Harper, Peter R., Leal, George R., Yong, Lois E., Tran, Tu Anh, Metz, Jeffrey W.
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US10/097,036
• Publication Number:
  US 20030173667A1
• Time in Patent Office: 1,042 Days
• Field of Search: 257785-786, 257/48, 257/780
• US Class Current: 257/786
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0392 specifically adapted to include a probing step
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.

Claims

1. An integrated circuit comprising:

a substrate having active circuitry and a perimeter;

a plurality of layers of interconnect over the substrate;

a final layer of interconnect over the plurality of layers of interconnect having a final layer pad and a plurality of interconnect lines, the final layer pad comprising copper;

a layer of passivation over the final layer of interconnect having an opening over the final layer pad; and

a bond pad comprising aluminum formed over and electrically contacting the final layer pad having a first region and a second region, wherein the first region is between the second region and the perimeter, the first and second regions are substantially non-overlapping and contiguous, and the first region performs a function of one of a probe region and a wire bond region and the second region performs the function of one of probe region and wire bond region not performed by the first region, wherein the bond pad is positioned directly over the active circuitry and over interconnect lines of the final layer of interconnect lines that are unrelated to the bond pad.

2. The integrated circuit of claim 1, wherein the opening has a first width and the bond pad extends over the surface of the layer of passivation past the opening in at least one direction by an amount greater than the first width.

3. The integrated circuit structure of claim 1, wherein the opening is filled with tantalum and aluminum.

4. The integrated circuit of claim 1 wherein the bond pad comprises a layer of barrier conductor on the layer of passivation and in the opening and a layer of pad metal over the barrier conductor.

5. The integrated circuit of claim 4, wherein the barrier conductor comprises tantalum and the pad metal layer comprises aluminum.

6. The integrated circuit of claim 4, wherein the barrier conductor is tantalum nitride.

7. The integrated circuit of claim 4, wherein the barrier conductor is selected from one or more of tantalum, titanium nitride, tantalum nitride, and titanium.

8. The integrated circuit of claim 4, wherein the barrier conductor comprises means for providing electrical conduction and adhesion between the final layer pad and the bond pad.

9. The integrated circuit of claim 4, wherein the pad metal is gold.

10. An integrated circuit, comprising:

a substrate having active circuitry and a perimeter;

a first plurality of interconnect layers over the substrate;

a plurality of final layer pads comprising copper over the first plurality of interconnect layers;

a passivation layer having a plurality of openings corresponding to the final layer pads; and

a plurality of bond pads comprising aluminum, coupled to the final layer pads through the openings, having first portions over the openings and second portions over the passivation layer, wherein the second portion is greater in area than the first portion, wherein the plurality of bond pads extend directly over the active circuitry and directly over interconnect lines of a final layer of interconnect lines that are unrelated to the plurality of bond pads, and wherein the second portion is significantly larger than the first portion, and wherein the first portion is for wire bonding and the second portion is for probing.

11. The integrated circuit of claim 10, wherein the plurality of bond pads each have first and second regions, wherein one of the first and second regions is for receiving a probe and the other of the first and second regions is for receiving a wire bond, wherein the first and second regions are substantially non-overlapping.