DC offset compensator

• US 6,844,690 B2
• Filed: 05/24/2002
• Issued: 01/18/2005
• Est. Priority Date: 05/24/2002
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Huggett, Colin, Kalman, Gabor
• Primary Examiner(s): Martin, David
• Assistant Examiner(s): SMITH, TYRONE W
• Application Number:
  US10/155,184
• Publication Number:
  US 20030218441A1
• Time in Patent Office: 970 Days
• Field of Search: 318/100, 318/798, 318/799, 318/800, 318/801, 318430-434, 318/521, 363/42, 363/48, 363/84, 363/89
• US Class Current: 318/100
• CPC Class Codes: H02M 7/53873 with digital control

Abstract

A dc offset compensator receives a three phase ac current signal as an input and provides a dc offset signal correction voltage as an output. The dc offset compensator comprises a processor configured to sample the ac current signal, generate a rotating vector (r) from the sample, extract a dc offset from the sample and to generate a dc offset signal correction voltage from the dc offset. A method of compensating for dc offset in a three phase ac current signal is also presented.

Claims

1. A method of compensating for dc offset in a three phase ac current signal, comprising the steps of:

providing a sample of the ac current signal;

generating a rotating vector (r) from the sample;

extracting a dc offset from the sample;

removing the dc offset from the ac current signal; and

generating a Park vector representing a total measured current vector (iT) from the sample using the formula;

iT=(⅔

)(Ia+(a)(Ib)+(a2)(Ic));

where a=exp(j2π

/3), Ia equals the amplitude of the phase current A (Ia=I sin(wt)), Ib equals the amplitude of the phase current B (Ib=I sin(wt+π

/3)) and Ic equals the amplitude of the phase current C (Ic=I sin(wt+2π

/3)) and w=frequency and t=time;

wherein the three phases of the ac current signal comprise a phase current A, a phase current B, and a phase current C.

2. The method of claim 1 wherein the step of generating a rotating vector (r) is carried out using the formula:

r=exp(jθ

*);

where θ

* equals a first estimated angle.

3. The method of claim 2 wherein the step of extracting a dc offset comprises the steps of:

subtracting a first estimated dc offset current vector (iDC*) from the total measured current vector (iT) to obtain a first estimated positive sequence current vector (iP*);

generating a vector cross product of the first estimated positive sequence current vector (iP*) and the rotating vector (r) to obtain an a vector cross product;

operating on the vector cross-product with a regulator to produce a signal proportional to the electrical frequency;

integrating the signal proportional to the electrical frequency to obtain a new estimated angle (θ

**);

using the new estimated angle (θ

**) in the step of generating a rotating vector (r);

subtracting the first estimated positive sequence current (iP*) from the total measured current (iT) to obtain an error signal;

multiplying the error signal by the complex conjugate of the rotator vector (r);

comparing the error signal to zero;

filtering the error signal to remove high frequency components so that the remaining signal is a dc voltage;

operating on the dc voltage signal with a regulator;

multiplying the output of the regulator by the rotating vector (r), thereby providing a new estimated positive sequence current (iP*);

subtracting the new estimated positive sequence current (iP*) from the total measured current vector (iT) to develop the first estimated dc offset current vector iDC* content of the ac current signal;

converting the first estimated dc offset current vector (iDC*) to a dc offset signal correction voltage indicative of the dc offset; and

outputting the dc offset signal correction voltage.

4. The method of claim 3 wherein PI regulators are used during each of the steps of regulating the ac current signal.

5. The method of claim 3 wherein the source of the ac current signal is an inverter and the dc offset signal correction voltage is conducted to the inverter.

6. A method of compensating for dc offset in a three phase ac current signal comprising a phase current A, a phase current B, and a phase current C and comprising the steps of:

sampling the ac current signal;

generating a rotating vector (r) from the sample using the formula;

r=exp(θ

*);

where θ

* equals a first estimated angle;

generating a Park vector representing a total measured current vector (iT) from the sample using the formula;

iT=(⅔

)(Ia+(a)(Ib)+(a2)(Ic));

where a=exp(j2π

/3), Ia equals the amplitude of the phase current A (Ia=I sin(wt)), Ib equals the amplitude of the phase current B (Ib=I sin(wt+π

/3)) and Ic equals the amplitude of the phase current C (Ic=I sin(wt+2π

/3)) and w=frequency and t=time;

extracting a dc offset from the sample by;

subtracting a first estimated dc offset current vector (iDC*) from the total measured current vector (iT) to obtain a first estimated positive sequence current vector (iP*);

generating a vector cross product of the first estimated positive sequence current vector (iP*) and the rotating vector (r) to obtain an a vector cross product;

integrating the vector cross product to obtain a second estimated angle θ

**;

using the new estimated angle θ

** in the step of generating a rotating vector (r);

subtracting the first estimated dc offset current vector (iDC**) from the total measured current vector (iT) to obtain a second estimated positive sequence current vector (iP**);

transforming the second estimated positive sequence current vector (iP**) from a stationary reference frame into a synchronous reference frame by multiplying the second estimated positive sequence current vector (iP**) by exp((j)(−

θ

**)) to obtain a transformed vector;

comparing the transformed vector to zero;

returning the transformed vector to the stationary reference frame by multiplying the transformed vector by exp(jθ

**) to again obtain the second estimated positive sequence current vector (iP**);

subtracting the second estimated positive sequence current vector (iP**) from the total measured current vector (iT) to obtain the first estimated dc offset current vector (iDC*);

comparing the first estimated dc offset current vector (iDC*) to zero;

converting the first estimated dc offset current vector (iDC*) to a dc offset signal correction voltage indicative of the dc offset;

outputting the dc offset signal correction voltage; and

removing the dc offset from the ac current signal by combining the dc offset signal correction voltage with the ac current signal.

7. The method of claim 6 wherein the source of the ac current signal is an inverter and the dc offset signal correction voltage is conducted to the inverter.

8. A dc offset compensator receiving as an input a three phase ac current signal comprising a phase current A, a phase current B, and a phase current C, and providing as an output a dc offset signal correction voltage, the compensator comprising:

a processor configured to sample the ac current signal, to generate a rotating vector (r) from the sample, extract a dc offset from the sample, to generate a dc offset signal correction voltage from the dc offset, and to generate a Park vector representing a total measured current vector (iT) from the sample;

wherein the processor generates a Park vector using the formula;

iT=(⅔

)(Ia+(a)(Ib)+(a2)(Ic));

where a=exp(j2π

/3), Ia equals the amplitude of the phase current A (Ia=I sin(wt)), Ib equals the amplitude of the phase current B (Ib=I sin(wt+π

/3)) and Ic equals the amplitude of the phase current C (Ic=I sin(wt+2π

/3)) and w=frequency and t=time.

9. The dc offset compensator of claim 8 wherein the processor generates a rotating vector (r) using the formula:

r=exp(θ

*);

where θ

* equals a first estimated angle.

10. A dc offset compensator of receiving a three phase ac current signal as an input and providing a dc offset signal correction voltage as an output, comprising:

a processor is configured to sample the ac current signal, to generate a rotating vector (r) from the sample, to extract a dc offset from the sample, and to generate a dc offset correction voltage from the dc offset,

wherein the processor is configured in a first block to;

generate a rotating vector (r) based on a first estimated angle (θ

*);

generate a Park vector representing the total measured current vector (iT) from the total measured current;

subtract an estimated a dc offset current vector (iDC*) from the total measured current vector (iT) to obtain a first estimated positive-sequence current vector (iP*);

calculate a vector cross product of the first positive-sequence current vector and the rotating vector (r); and

integrate the vector cross product and output a second estimated angle (θ

**);

the processor is configured in a second block to receive the total measured current vector (iT) and the estimated angle (θ

**) and to;

subtract the first estimated positive sequence current (iP*) from the total measured current (iT) to obtain an error signal;

multiply the error signal by the complex conjugate of the rotator vector (r);

compare the error signal to zero;

filter the error signal to remove high frequency components so that the remaining signal is a dc voltage;

operate on the dc voltage signal with a regulator;

multiply the output of the regulator by the rotating vector (r), thereby providing a new estimated positive sequence current (iP*);

subtract the new estimated positive sequence current (iP*) from the total measured current vector (iT) to develop the first estimated dc offset current vector iDC* content of the ac current signal;

convert the first estimated dc offset current vector (iDC*) to a dc offset signal correction voltage indicative of the dc offset; and

output the dc offset signal correction voltage.

11. A dc offset compensator receiving a three phase signal from a source and providing a correction signal to an inverter, comprising:

an input for receiving a total measured current from the source;

a processor connected to the input and configured in a first block to;

generate a rotating vector (r) based on a first estimated angle (θ

*);

generate a Park vector representing the total measured current vector (iT) from the total measured current;

subtract an estimated a dc offset current vector (iDC*) from the total measured current vector (iT) to obtain a first estimated positive-sequence current vector (iP*);

calculate a vector cross product of the first positive-sequence current vector and the rotating vector (r); and

integrate the vector cross product and output a second estimated angle (θ

**);

the processor configured in a second block to receive the total measured current vector (iT) and the estimated angle (θ

**) and to;

subtract the first estimated positive sequence current (iP*) from the total measured current (iT) to obtain an error signal;

multiply the error signal by the complex conjugate of the rotator vector (r);

compare the error signal to zero;

filter the error signal to remove high frequency components so that the remaining signal is a dc voltage;

operate on the dc voltage signal with a regulator;

multiply the output of the regulator by the rotating vector (r), thereby providing a new estimated positive sequence current (iP*);

subtract the new estimated positive sequence current (iP*) from the total measured current vector (iT) to develop the first estimated dc offset current vector iDC* content of the ac current signal;

convert the first estimated dc offset current vector (iDC*) to a dc offset signal correction voltage indicative of the dc offset; and

output the dc offset signal correction voltage

the processor configured in a third block to receive the total measured current vector (iT) and the estimated angle (θ

**) and to;

compare the first estimated dc offset current vector (iDC*) to zero; and

convert the first estimated dc offset current vector (iDC*) to a voltage correction signal for input to the inverter.

12. The dc offset compensator of claim 11 wherein:

the three phases of the ac current signal comprise a phase current A, a phase current B, and a phase current C; and

the processor generates a Park vector using the formula;

iT=(⅔

)(Ia+(a)(Ib)+(a2)(Ic));

where a=exp(j2π

/3), Ia equals the amplitude of the phase current A (Ia=I sin(wt)), Ib equals the amplitude of the phase current B (Ib=I sin(wt+π

/3)) and Ic equals the amplitude of the phase current C (Ic=I sin(wt+2π

/3)) and w=frequency and t=time.

13. The dc offset compensator of claim 11 wherein the processor generates a rotating vector (r) using the formula:

r=exp(θ

*);

where θ

* equals a first estimated angle.

14. The dc offset compensator of claim 11 wherein the processor is further configured in the first block to utilize a PI regulator configured to produce a signal proportional to the electrical frequency of the cross product.

15. The dc offset compensator of claim 11 wherein the processor is further configured in the second block to utilize a PI regulator to produce a signal proportional to the electrical frequency of the dc voltage signal.

16. The dc offset compensator of claim 12 wherein the processor is further configured to produce a dc voltage offset signal.