×

Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting

  • US 6,844,747 B2
  • Filed: 03/19/2001
  • Issued: 01/18/2005
  • Est. Priority Date: 03/19/2001
  • Status: Expired due to Fees
First Claim
Patent Images

1. A method for electrically stressing through a specified voltage at least one semiconductor chip on a wafer for controlled contactless burn-in, voltage screen and reliability evaluation of product wafers, said method comprising:

  • applying said voltage to said at least one chip for the probing thereof in the absence of physically contacting the chip surface; and

    interposing a mask comprising a metallic wiring line layer forming a wire loop on said wafer for magnetically inducing said voltage from ends of the wire loop providing electrical connections to said at least one chip, said mask having the voltage induced thereto when placed in a magnetic field and thereafter conducted to electrical contacts on said wafer.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×