Wafer level system for producing burn-in/screen, and reliability evaluations to be performed on all chips simultaneously without any wafer contacting
First Claim
1. A method for electrically stressing through a specified voltage at least one semiconductor chip on a wafer for controlled contactless burn-in, voltage screen and reliability evaluation of product wafers, said method comprising:
- applying said voltage to said at least one chip for the probing thereof in the absence of physically contacting the chip surface; and
interposing a mask comprising a metallic wiring line layer forming a wire loop on said wafer for magnetically inducing said voltage from ends of the wire loop providing electrical connections to said at least one chip, said mask having the voltage induced thereto when placed in a magnetic field and thereafter conducted to electrical contacts on said wafer.
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Accused Products
Abstract
A wafer level system for producing burn-in, voltages screen, and reliability evaluations which are to be performed on all wafers simultaneously without necessitating the probe contacting of any wafer during burn-in/stress. Also provided is a method for implementing the wafer level product burn-in/screen, and semiconductor reliability evaluations on semiconductor chips pursuant to the wafer level system. Pursuant to a preferred aspect all chips of a wafer are stressed simultaneously without having a probe physically contact any chip during the stress procedure. This concept can be applied to burn-in of product wafers, voltage screen of product wafers, and reliability evaluations of various failure mechanisms.
28 Citations
50 Claims
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1. A method for electrically stressing through a specified voltage at least one semiconductor chip on a wafer for controlled contactless burn-in, voltage screen and reliability evaluation of product wafers, said method comprising:
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applying said voltage to said at least one chip for the probing thereof in the absence of physically contacting the chip surface; and
interposing a mask comprising a metallic wiring line layer forming a wire loop on said wafer for magnetically inducing said voltage from ends of the wire loop providing electrical connections to said at least one chip, said mask having the voltage induced thereto when placed in a magnetic field and thereafter conducted to electrical contacts on said wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A system for electrically stressing through a specified voltage at least one semiconductor chip on a wafer for controlled contactless burn-in, voltage screen and
reliability evaluation of product wafers, said system comprising: -
a circuit for applying said voltage to said at least one chip for the probing thereof in the absence of physically contacting the chip surface; and
a mask comprising a metallic wiring line layer forming a wire loop being arranged on said wafer through which said voltage is magnetically induced and applied to said at least one chip from ends of said wire loop providing electrical connections through the interposition of said mask onto which the voltage is induced when placed in a magnetic field and thereafter conducted to electrical contacts on said wafer. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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Specification