Digital to analog converter having a low power semi-analog finite impulse response circuit

• US 6,844,838 B2
• Filed: 05/22/2003
• Issued: 01/18/2005
• Est. Priority Date: 05/22/2003
• Status: Expired due to Fees

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Mallinson, Andrew Martin
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/444,813
• Publication Number:
  US 20040233088A1
• Time in Patent Office: 607 Days
• Field of Search: 341/154, 341/143, 341/144
• US Class Current: 341/144
• CPC Class Codes: H03M 3/504 the final digital/analogue converter being constituted by a finite impulse response [FIR] filter, i.e. FIRDAC

Abstract

A circuit is provided having a secondary semi-analog FIR filter connected to a primary filter via a coefficient to reduce the size of the sizes of the resistors used in the primary filter. The coefficient may be one or more intermediate resistors connected between separate resistor/voltage driver banks that make up the FIR filter. The result is a circuit that takes up less chip space required to accommodate the required resistance for a digital to analog converter (DAC). The invention configures the resistor structure to produce the same output result as a conventional circuit, but with smaller resistor values that take up less surface area on the chip.

Claims

1. A semi-analog FIR digital to analog converter comprising:

an input configured to receive a digital signal input;

an output configured to transmit an impulse signal corresponding to the digital signal input;

a primary finite impulse response circuit having a plurality of voltage sources corresponding to a bank of resistor values;

a secondary finite impulse response circuit having a plurality of voltage sources corresponding to a plurality of intermediate resistors, wherein the secondary circuit is connected to the primary circuit via the plurality of intermediate resistors connected in parallel with certain resistors in the bank of resistors and configure to reduce the dynamic range of resistor values in the semi-analog FIR DAC and is connected to the output to produce an impulse output signal.

2. A digital to analog converter according to claim 1, wherein the secondary circuit is a Thevenin equivalent of a portion of the primary circuit.

3. A digital to analog converter according to claim 1, wherein the configured circuit is a Thevenin equivalent of a portion of the primary circuit.

4. A circuit according to claim 1, where in the secondary finite impulse response circuit shares the same plurality of voltage sources as the primary finite impulse response circuit, wherein the secondary circuit is connected to the primary finite impulse response circuit via a bank of intermediate resistors and is also connected to the output to produce an analog output signal corresponding to the digital input signal.

5. A converter according to claim 1, wherein the plurality of voltage sources correspond to the plurality of resistors, wherein the secondary circuit is connected to the primary circuit via an intermediate resistor circuit and wherein pairs of resistors having equal values are connected together in parallel with and then connected in parallel with other resistors with an intermediate resistor.

6. A digital to analog converter comprising:

an input configured to receive a digital signal input signal;

a primary finite impulse response circuit having a plurality of voltage sources corresponding to a plurality of resistors connected in parallel and in a parabolic manner;

a secondary finite impulse response circuit having a plurality of voltage sources corresponding to a plurality of resistor values, wherein the secondary circuit is connected to the primary circuit via an intermediate resistor circuit, and wherein pairs of resistors having equal values are connected together in parallel with and then connected in parallel with other resistors with an intermediate resistor; and

an output connected to the intermediate resistor and configured to transmit an impulse signal corresponding to the digital input signal.

7. A circuit according to claim 6, where in the secondary finite impulse response circuit shares the same plurality of voltage sources as the primary finite impulse response circuit, wherein the secondary circuit is connected to the primary finite impulse response circuit via a bank of intermediate resistors and is also connected to the output to produce an analog output signal corresponding to the digital input signal.

8. A semi-analog finite impulse response digital to analog converter (“

semi-analog FIR DAC”

) comprising;

an input configured to receive a digital signal input;

an output configured to transmit an impulse signal corresponding to the digital signal input; and

a finite impulse response circuit having a plurality of voltage sources corresponding to a plurality of resistors connected in a parallel with each other and a circuit having at least one pair of resistors connected together and to an intermediate resistor at a common node at one end of the intermediate resistor in a manner to reduce the dynamic range of resistor values in the semi-analog FIR DAC, where the resistor is connected at another end to the output to produce an impulse output signal.

9. A semi-analog finite impulse response digital to analog converter comprising:

an input configured to receive a digital signal input signal;

a bank of flip-flops clocked in synchronicity;

a bank of voltage sources connected to the bank of flip-flops;

a plurality of resistors having a range of resistance values and connected to the plurality of voltage sources in a Thevenin equivalent manner to reduce the dynamic range of resistance values required of a bank of resistors connected in parallel to produce an equivalent impulse signal output in response to a digital input signal.

10. A converter according to claim 9, wherein each flip flop from the bank of flip-flops corresponds with a voltage source from the bank of voltage sources, wherein each flip flop is configured to enable its corresponding voltage source alternately with other flip flops in the bank of flip flops.

11. A converter according to claim 9, wherein each flip flop from the bank of flip-flops corresponds with a voltage source from the bank of voltage sources, wherein each flip flop is configured to enable its corresponding voltage source alternately with other flip flops in the bank of flip flops to apply a voltage across resistors connected to the corresponding voltage source.

12. A converter according to claim 9, wherein the bank of voltage sources correspond to the plurality of resistors, wherein the secondary circuit is connected to the primary circuit via an intermediate resistor circuit, and wherein pairs of resistors having equal values are connected together in parallel with and then connected in parallel with other resistors with an intermediate resistor.