Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems
First Claim
1. A nonvolatile semiconductor memory comprising:
- a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;
a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and
a first select gate line connected to each of the gate electrodes of the first select transistors, wherein the plurality of the word lines have a wiring line width which is the same as the first select gate line.
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Accused Products
Abstract
A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.
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Citations
71 Claims
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1. A nonvolatile semiconductor memory comprising:
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a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a source region, a drain region, a gate electrode and a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;
a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and
a first select gate line connected to each of the gate electrodes of the first select transistors, wherein the plurality of the word lines have a wiring line width which is the same as the first select gate line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 68)
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25. A semiconductor integrated circuit, comprising,
a semiconductor chip; -
a semiconductor memory mounted on the semiconductor chip comprising;
a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a charge storage layer, disposed in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;
a plurality of first select transistors selecting the memory cell transistors, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and
a first select gate line connected to each of the gate electrode of the first select transistors; and
a logic circuit mounted on the semiconductor chip to control the semiconductor memory, wherein the plurality of the word lines have a wiring line width which is the same as the first select gate line. - View Dependent Claims (26, 69)
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27. A system for storing information and for accessing a storage medium comprising:
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a memory card including a semiconductor memory comprises, a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a charge storage layer, disposed in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;
a plurality of first select transistors selecting the memory cell transistors, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and
a first select gate line connected to each of the gate electrode of the first select transistors, wherein the plurality of the word lines have a wiring line width which is the same as the first select gate line. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 70)
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49. A system for storing information and for accessing a storage medium comprising:
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an IC card board;
a semiconductor memory disposed on the IC card board, comprising;
a plurality of word lines disposed in a row direction;
a plurality of bit lines disposed in a column direction perpendicular to the word lines;
memory cell transistors having a charge storage layer, disposed in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell;
a plurality of first select transistors selecting the memory cell transistors disposed in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors disposed in the column direction; and
a first select gate line connected to each of the gate electrodes of the first select transistors, wherein the plurality of the word lines have a wiring line width which is the same as the first select gate line. - View Dependent Claims (50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 71)
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Specification