Dual reference cell sensing scheme for non-volatile memory

• US 6,845,052 B1
• Filed: 05/30/2003
• Issued: 01/18/2005
• Est. Priority Date: 05/30/2003
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Liou, Ho-Chun, Chen, Gin-Liang, Hung, Chun-Hsiung, Ho, Wen-Chiao, Ho, Hsin-Yi, Kuo, Nai-Ping
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/250,040
• Publication Number:
  US 20040264249A1
• Time in Patent Office: 599 Days
• Field of Search: 365/210, 365/189.08, 365/207, 365/196
• US Class Current: 365/149
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.

Claims

1. A high speed non-volatile memory device, comprising:

at least one memory cell;

a first reference cell;

a second reference cell;

a first sense amplifier coupled to the first reference cell and the memory cell for determining a voltage difference between the first reference cell and the memory cell;

a second sense amplifier coupled to the second reference cell and the memory cell for determining a voltage difference between the second reference cell and the memory cell; and

a third sense amplifier coupled to the first sense amplifier and the second sense amplifier for determining a status of the memory cell according to the voltage differences of the first sense amplifier and the second sense amplifier.

2. The device in claim 1, wherein the first reference cell comprises a current source and a capacitor for generating a first voltage reference signal.

3. The device in claim 1, wherein the second reference cell comprises a current source and a capacitor for generating a second voltage reference signal.

4. The device in claim 1, wherein the first reference cell comprises a current source and a resistor connected to VDD for generating a first voltage reference signal.

5. The device in claim 1, wherein the second reference cell comprises a current source and a resistor connected to VDD for generating a second voltage reference signal.

6. The device in claim 1, wherein the first reference cell is connected to ground and the second reference cell comprises a current source and a resistor connected to VDD for generating a first voltage reference signal.

7. The device in claim 1, wherein each of the first reference cell and the second reference cell is a single reference cell.

8. A high speed non-volatile memory device, comprising:

at least one memory cell;

a first reference cell comprising a current source and a capacitor;

a second reference cell comprising a current source and a capacitor;

a first sense amplifier coupled to the first reference cell and the memory cell for determining a voltage difference between the first reference cell and the memory cell;

a second sense amplifier coupled to the second reference cell and the memory cell for determining a voltage difference between the second reference cell and the memory cell; and

a third sense amplifier coupled to the first sense amplifier and the second sense amplifier for determining a status of the memory cell according to the voltage differences of the first sense amplifier and the second sense amplifier.

9. The device in claim 8, wherein each of the first reference cell and the second reference cell is a single reference cell.

10. The device in claim 8, wherein the memory cell includes a current source and a capacitor.

11. A high speed non-volatile memory device, comprising:

at least one memory cell;

a first reference cell comprising a current source and a resistor connected to VDD;

a second reference cell comprising a current source and a resistor connected to VDD;

a first sense amplifier coupled to the first reference cell and the memory cell for determining a voltage difference between the first reference cell and the memory cell;

a second sense amplifier coupled to the second reference cell and the memory cell for determining a voltage difference between the second reference cell and the memory cell; and

a third sense amplifier coupled to the first sense amplifier and the second sense amplifier for determining a status of the memory cell according to the voltage differences of the first sense amplifier and the second sense amplifier.

12. The device in claim 11, wherein each of the first reference cell and the second reference cell is a single reference cell.

13. A high speed non-volatile memory device, comprising:

at least one memory cell;

a first reference cell coupled to ground;

a second reference cell comprising a current source and a resistor connected to VDD;

a first sense amplifier coupled to the first reference cell and the memory cell for determining a voltage difference between the first reference cell and the memory cell;

a second sense amplifier coupled to the second reference cell and the memory cell for determining a voltage difference between the second reference cell and the memory cell; and

a third sense amplifier coupled to the first sense amplifier and the second sense amplifier for determining a status of the memory cell according to the voltage differences of the first sense amplifier and the second sense amplifier.

14. The device in claim 13, wherein each of the first reference cell and the second reference cell is a single reference cell.

15. A method for sensing a non-volatile memory with dual reference cells, comprising:

providing first sense amplifier, a second sense amplifier, and a third sense amplifier, wherein each of the sense amplifiers has a first polarity input terminal and a second polarity input terminal;

applying a first voltage reference signal to the first polarity input terminal of the first sense amplifier, and a second voltage reference signal to the second polarity input terminal of the second sense amplifier;

applying a cell reference signal, which is to be sensed, to the second polarity input terminal of the first sense amplifier and the first polarity input terminal of the second sense amplifier, and

leading outputs of the first sense amplifier and the second sense amplifier to the third sense amplifier.

16. The method of claim 15, wherein the first polarity input terminal is a negative input terminal and the second polarity input terminal is a positive input terminal.

17. The method of claim 15, wherein the first polarity input terminal is a positive input terminal and the second polarity input terminal is a negative input terminal.

18. The method of claim 15, wherein the first voltage reference signal is from a high voltage reference cell.

19. The method of claim 15, wherein the high voltage reference cell is a ground voltage, a floating ground, or a reference current source.

20. The method of claim 15, wherein the second voltage reference signal is from a low voltage reference cell.