Analog peak detection circuitry for radio receivers

• US 6,845,232 B2
• Filed: 05/03/2002
• Issued: 01/18/2005
• Est. Priority Date: 03/25/2002
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Darabi, Hooman
• Primary Examiner(s): Vo, Nguyen
• Assistant Examiner(s): Le, Nhan T
• Application Number:
  US10/138,675
• Publication Number:
  US 20030181175A1
• Time in Patent Office: 991 Days
• Field of Search: 455/136, 455/226.1, 455/226.2, 455/232.1, 455/240.1, 455/245.1, 455/250.1, 455/263, 455/247.1, 455/293, 455/309, 455/252.1, 327/58, 327/59, 327/62, 327/359, 330/253, 330/257, 330/277, 330/288, 375/345
• US Class Current: 455/240.1
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence

Abstract

A receiver portion of a radio includes an analog circuit for determining a peak amplitude in a way that eliminates or reduces the effects of frequency errors that are introduced by crystals within filters and other devices. A voltage follower and a current mirror in which a MOSFET coupled to an output node produces a voltage across its gate to source terminals whose value is a function of a sum of the gate to source voltages of two MOSFET devices that receive a logarithm of an I modulated channel and a logarithm of a Q modulated channel, respectively.

Claims

1. A radio receiver formed in an integrated circuit, comprising:

a low noise amplifier (LNA) coupled to receive an RF signal from an antenna, the LNA for providing amplification of the RF signal in accordance with control commands;

a mixer coupled to receive an amplified RF signal from the LNA, the mixer for down converting the amplified RF signal into I and Q modulated channels;

an analog peak amplitude detection circuit further comprising;

log circuitry for producing an output characterized by the log(x), the log circuitry coupled to receive the I and Q modulated channels and for producing log(I) and log(Q) modulated channel signals;

dual input nodes coupled to receive the log(I) and log(Q) modulated channel signals from the log circuitry, one at each input of the dual input nodes;

a voltage follower configuration wherein an output signal of the analog peak amplitude detection circuit is a function of the sum of the log(I) and log(Q) modulated channel signals; and

gain control circuitry coupled to receive the output signal and to produce therefrom the control commands.

2. The radio receiver of claim 1 wherein the peak detection circuit further includes a current sink coupled to a circuit common wherein the dual input nodes are each coupled to a gate terminal of a pair of input MOSFETs each also having a drain terminal and a source terminal, the input MOSFETs coupled in parallel and wherein the source terminals of the input MOSFETs are coupled to the current sink.

3. The radio receiver of claim 2 further including an output MOSFET coupled in a voltage follower configuration wherein the output MOSFET includes a gate terminal coupled to a drain terminal of the output MOSFET and to an output port of the analog peak amplitude detection circuit and further includes a source terminal of the output MOSFET coupled to the current sink.

4. The radio receiver of claim 3 further including a current mirror formed of a first current mirror MOSFET and a second current mirror MOSFET, wherein the first current mirror MOSFET includes a source terminal that is coupled to a voltage source, and a gate terminal and a drain terminal that are both coupled to the drain terminals of the pair of input MOSFETs of the dual input nodes.

5. The radio receiver of claim 4 wherein the second current mirror MOSFET comprises a gate terminal coupled to the gate terminal and drain terminal of the first current mirror MOSFET and a source terminal coupled to the voltage source and a drain terminal coupled to a drain terminal of the output MOSFET.

6. The radio receiver of claim 5 wherein the output signal is a function of a sum of gate to source terminal voltage levels for the input MOSFETs.

7. The radio receiver of claim 6 wherein a gate to source voltage of the output MOSFET is equal to or exceeds the gate to source voltage levels of at least one of the two input MOSFETs.

8. The radio receiver of claim 7 wherein the gate to source voltage level of the output MOSFET is equal to a square root of (2) times an amplitude of at least one of the gate to source voltage levels of the input MOSFETs.

9. An analog peak amplitude detection circuit formed within a radio receiver for detecting a peak of a modulated signal, comprising:

log circuitry for producing a logarithm of an I modulated channel signal and of a Q modulated channel signal;

first and second input MOSFETs, each having a gate terminal, a source terminal and a drain terminal, the first input MOSFET coupled to receive the logarithm of the I modulated channel signal at the gate terminal of the first input MOSFET, and the second input MOSFET coupled to receive the logarithm of the Q modulated channel signal at the gate terminal of the second input MOSFET;

an output node of the analog peak amplitude detection circuit;

an output MOSFET having a gate terminal, a source terminal and a drain terminal wherein the drain terminal and the gate terminal of the output MOSFET are coupled to the output node of the analog peak amplitude detection circuit;

a current drain coupled to sink current from the source terminals of the first and second input MOSFETs and the output MOSFET; and

a current mirror coupled between a voltage source and the drain terminals of the first and second input MOSFETs and the drain terminal of the output MOSFET.

10. The analog peak amplitude detection circuit of claim 9 wherein the current mirror comprises a first and second current mirror MOSFET, each of the at least two MOSFETs having gate terminals wherein the gate terminals of the first and second current mirror MOSFETs are coupled together and to the drain terminals of the first and second input MOSFETs.

11. The analog peak amplitude detection circuit of claim 10 wherein the first and second current mirror MOSFETs are p-channel enhancement MOSFETs and wherein the first and second input MOSFETs and the output MOSFET are n-channel enhancement MOSFETs.

12. The analog peak amplitude detection circuit of claim 11 wherein the first and second current mirror MOSFETs further include source terminals coupled to a voltage source.

13. The analog peak amplitude detection circuit of claim 11 wherein a current conducted through the first current mirror MOSFET is reflected in the second current mirror MOSFET.

14. The analog peak amplitude detection circuit of claim 11 wherein a current conducted through the first current mirror MOSFET is reflected in a third current mirror MOSFET coupled to the first and second current mirror MOSFETs.

15. The analog peak amplitude detection circuit of claim 13 wherein an amount of current conducted through the second current mirror MOSFET is conducted into the output node.

16. The analog peak amplitude detection circuit of claim 15 wherein the amount of current conducted through the output node is approximately equal to the amount of current conducted through the first and second input MOSFETs.

17. A method for detecting a peak voltage in an analog circuit, comprising:

receiving a logarithm of an I modulated channel signal having a first amplitude at a gate terminal of a first input MOSFET, the first input MOSFET having a gate, a source and a drain terminal;

receiving a logarithm of a Q modulated channel signal having a second amplitude at a gate terminal of a second input MOSFET, the second input MOSFET having a gate, a source and a drain terminal; and

producing an output signal across an output MOSFET'"'"'s gate and source terminals wherein the output MOSFET'"'"'s gate terminal is coupled to an output node, the output signal having an amplitude that is a function of a sum of an amplitude of a signal formed across the gate to source terminals of the first and second input MOSFETs.

18. The method of claim 17 further including the step of conducting approximately equal amounts of total current conducted through the input MOSFETs and through the output node.

19. The method of claim 17 further comprising sinking all of the current conducted through the first output MOSFET through a current sink.

20. The method of claim 18 further including sinking at least some of the current conducted through the output node through the current sink.

21. The method of claim 18 further comprising sinking all of the current conducted through the output node and through the output MOSFET wherein the current in the output MOSFET is equal to the total current conducted through the input MOSFETs.